1 /* 2 * (C) Copyright 2013 Atmel Corporation 3 * Josh Wu <josh.wu@atmel.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/at91sam9x5_matrix.h> 11 #include <asm/arch/at91sam9_smc.h> 12 #include <asm/arch/at91_common.h> 13 #include <asm/arch/at91_rstc.h> 14 #include <asm/arch/at91_pio.h> 15 #include <asm/arch/clk.h> 16 #include <lcd.h> 17 #include <atmel_hlcdc.h> 18 #include <atmel_mci.h> 19 #include <netdev.h> 20 21 #ifdef CONFIG_LCD_INFO 22 #include <nand.h> 23 #include <version.h> 24 #endif 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 /* ------------------------------------------------------------------------- */ 29 /* 30 * Miscelaneous platform dependent initialisations 31 */ 32 #ifdef CONFIG_NAND_ATMEL 33 static void at91sam9n12ek_nand_hw_init(void) 34 { 35 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 36 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 37 unsigned long csa; 38 39 /* Assign CS3 to NAND/SmartMedia Interface */ 40 csa = readl(&matrix->ebicsa); 41 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 42 /* Configure databus */ 43 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */ 44 /* Configure IO drive */ 45 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 46 47 writel(csa, &matrix->ebicsa); 48 49 /* Configure SMC CS3 for NAND/SmartMedia */ 50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 51 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 52 &smc->cs[3].setup); 53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 54 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 55 &smc->cs[3].pulse); 56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7), 57 &smc->cs[3].cycle); 58 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 59 AT91_SMC_MODE_EXNW_DISABLE | 60 #ifdef CONFIG_SYS_NAND_DBW_16 61 AT91_SMC_MODE_DBW_16 | 62 #else /* CONFIG_SYS_NAND_DBW_8 */ 63 AT91_SMC_MODE_DBW_8 | 64 #endif 65 AT91_SMC_MODE_TDF_CYCLE(1), 66 &smc->cs[3].mode); 67 68 /* Configure RDY/BSY pin */ 69 at91_set_pio_input(AT91_PIO_PORTD, 5, 1); 70 71 /* Configure ENABLE pin for NandFlash */ 72 at91_set_pio_output(AT91_PIO_PORTD, 4, 1); 73 74 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 75 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 76 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ 77 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ 78 } 79 #endif 80 81 #ifdef CONFIG_LCD 82 vidinfo_t panel_info = { 83 .vl_col = 480, 84 .vl_row = 272, 85 .vl_clk = 9000000, 86 .vl_bpix = LCD_BPP, 87 .vl_sync = 0, 88 .vl_tft = 1, 89 .vl_hsync_len = 5, 90 .vl_left_margin = 8, 91 .vl_right_margin = 43, 92 .vl_vsync_len = 10, 93 .vl_upper_margin = 4, 94 .vl_lower_margin = 12, 95 .mmio = ATMEL_BASE_LCDC, 96 }; 97 98 void lcd_enable(void) 99 { 100 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ 101 } 102 103 void lcd_disable(void) 104 { 105 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */ 106 } 107 108 #ifdef CONFIG_LCD_INFO 109 void lcd_show_board_info(void) 110 { 111 ulong dram_size, nand_size; 112 int i; 113 char temp[32]; 114 115 lcd_printf("%s\n", U_BOOT_VERSION); 116 lcd_printf("ATMEL Corp\n"); 117 lcd_printf("at91@atmel.com\n"); 118 lcd_printf("%s CPU at %s MHz\n", 119 ATMEL_CPU_NAME, 120 strmhz(temp, get_cpu_clk_rate())); 121 122 dram_size = 0; 123 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 124 dram_size += gd->bd->bi_dram[i].size; 125 nand_size = 0; 126 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 127 nand_size += nand_info[i].size; 128 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 129 dram_size >> 20, 130 nand_size >> 20); 131 } 132 #endif /* CONFIG_LCD_INFO */ 133 #endif /* CONFIG_LCD */ 134 135 /* SPI chip select control */ 136 #ifdef CONFIG_ATMEL_SPI 137 #include <spi.h> 138 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 139 { 140 return bus == 0 && cs < 2; 141 } 142 143 void spi_cs_activate(struct spi_slave *slave) 144 { 145 switch (slave->cs) { 146 case 0: 147 at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 148 break; 149 case 1: 150 at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 151 break; 152 } 153 } 154 155 void spi_cs_deactivate(struct spi_slave *slave) 156 { 157 switch (slave->cs) { 158 case 0: 159 at91_set_pio_output(AT91_PIO_PORTA, 14, 1); 160 break; 161 case 1: 162 at91_set_pio_output(AT91_PIO_PORTA, 7, 1); 163 break; 164 } 165 } 166 #endif /* CONFIG_ATMEL_SPI */ 167 168 #ifdef CONFIG_GENERIC_ATMEL_MCI 169 int board_mmc_init(bd_t *bd) 170 { 171 at91_mci_hw_init(); 172 173 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); 174 } 175 #endif 176 177 #ifdef CONFIG_KS8851_MLL 178 void at91sam9n12ek_ks8851_hw_init(void) 179 { 180 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 181 182 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 183 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 184 &smc->cs[2].setup); 185 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 186 AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), 187 &smc->cs[2].pulse); 188 writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), 189 &smc->cs[2].cycle); 190 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 191 AT91_SMC_MODE_EXNW_DISABLE | 192 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 193 AT91_SMC_MODE_TDF_CYCLE(1), 194 &smc->cs[2].mode); 195 196 /* Configure NCS2 PIN */ 197 at91_set_b_periph(AT91_PIO_PORTD, 19, 0); 198 } 199 #endif 200 201 #ifdef CONFIG_USB_ATMEL 202 void at91sam9n12ek_usb_hw_init(void) 203 { 204 at91_set_pio_output(AT91_PIO_PORTB, 7, 0); 205 } 206 #endif 207 208 int board_early_init_f(void) 209 { 210 at91_periph_clk_enable(ATMEL_ID_PIOAB); 211 at91_periph_clk_enable(ATMEL_ID_PIOCD); 212 213 at91_seriald_hw_init(); 214 return 0; 215 } 216 217 int board_init(void) 218 { 219 /* adress of boot parameters */ 220 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 221 222 #ifdef CONFIG_NAND_ATMEL 223 at91sam9n12ek_nand_hw_init(); 224 #endif 225 226 #ifdef CONFIG_ATMEL_SPI 227 at91_spi0_hw_init(1 << 0); 228 #endif 229 230 #ifdef CONFIG_LCD 231 at91_lcd_hw_init(); 232 #endif 233 234 #ifdef CONFIG_KS8851_MLL 235 at91sam9n12ek_ks8851_hw_init(); 236 #endif 237 238 #ifdef CONFIG_USB_ATMEL 239 at91sam9n12ek_usb_hw_init(); 240 #endif 241 242 return 0; 243 } 244 245 #ifdef CONFIG_KS8851_MLL 246 int board_eth_init(bd_t *bis) 247 { 248 return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); 249 } 250 #endif 251 252 int dram_init(void) 253 { 254 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 255 CONFIG_SYS_SDRAM_SIZE); 256 return 0; 257 } 258 259 #if defined(CONFIG_SPL_BUILD) 260 #include <spl.h> 261 #include <nand.h> 262 263 void at91_spl_board_init(void) 264 { 265 #ifdef CONFIG_SYS_USE_MMC 266 at91_mci_hw_init(); 267 #elif CONFIG_SYS_USE_NANDFLASH 268 at91sam9n12ek_nand_hw_init(); 269 #elif CONFIG_SYS_USE_SPIFLASH 270 at91_spi0_hw_init(1 << 4); 271 #endif 272 } 273 274 #include <asm/arch/atmel_mpddrc.h> 275 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 276 { 277 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 278 279 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 280 ATMEL_MPDDRC_CR_NR_ROW_13 | 281 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 282 ATMEL_MPDDRC_CR_NB_8BANKS | 283 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); 284 285 ddr2->rtr = 0x411; 286 287 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 288 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 289 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 290 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 291 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 292 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 293 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 294 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 295 296 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 297 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 298 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 299 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 300 301 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 302 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 303 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 304 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 305 } 306 307 void mem_init(void) 308 { 309 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 310 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 311 struct atmel_mpddrc_config ddr2; 312 unsigned long csa; 313 314 ddr2_conf(&ddr2); 315 316 /* enable DDR2 clock */ 317 writel(AT91_PMC_DDR, &pmc->scer); 318 319 /* Chip select 1 is for DDR2/SDRAM */ 320 csa = readl(&matrix->ebicsa); 321 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 322 csa &= ~AT91_MATRIX_EBI_DBPU_OFF; 323 csa |= AT91_MATRIX_EBI_DBPD_OFF; 324 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 325 writel(csa, &matrix->ebicsa); 326 327 /* DDRAM2 Controller initialize */ 328 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); 329 } 330 #endif 331