19e336903SWu, Josh /* 29e336903SWu, Josh * (C) Copyright 2013 Atmel Corporation 39e336903SWu, Josh * Josh Wu <josh.wu@atmel.com> 49e336903SWu, Josh * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 69e336903SWu, Josh */ 79e336903SWu, Josh 89e336903SWu, Josh #include <common.h> 99e336903SWu, Josh #include <asm/io.h> 109e336903SWu, Josh #include <asm/arch/at91sam9x5_matrix.h> 119e336903SWu, Josh #include <asm/arch/at91sam9_smc.h> 129e336903SWu, Josh #include <asm/arch/at91_common.h> 139e336903SWu, Josh #include <asm/arch/at91_pmc.h> 149e336903SWu, Josh #include <asm/arch/at91_rstc.h> 159e336903SWu, Josh #include <asm/arch/at91_pio.h> 169e336903SWu, Josh #include <asm/arch/clk.h> 179e336903SWu, Josh #include <lcd.h> 189e336903SWu, Josh #include <atmel_hlcdc.h> 199e336903SWu, Josh #include <atmel_mci.h> 2016276220SBo Shen #include <netdev.h> 219e336903SWu, Josh 229e336903SWu, Josh #ifdef CONFIG_LCD_INFO 239e336903SWu, Josh #include <nand.h> 249e336903SWu, Josh #include <version.h> 259e336903SWu, Josh #endif 269e336903SWu, Josh 279e336903SWu, Josh DECLARE_GLOBAL_DATA_PTR; 289e336903SWu, Josh 299e336903SWu, Josh /* ------------------------------------------------------------------------- */ 309e336903SWu, Josh /* 319e336903SWu, Josh * Miscelaneous platform dependent initialisations 329e336903SWu, Josh */ 339e336903SWu, Josh #ifdef CONFIG_NAND_ATMEL 349e336903SWu, Josh static void at91sam9n12ek_nand_hw_init(void) 359e336903SWu, Josh { 369e336903SWu, Josh struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 379e336903SWu, Josh struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 389e336903SWu, Josh unsigned long csa; 399e336903SWu, Josh 409e336903SWu, Josh /* Assign CS3 to NAND/SmartMedia Interface */ 419e336903SWu, Josh csa = readl(&matrix->ebicsa); 429e336903SWu, Josh csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 439e336903SWu, Josh /* Configure databus */ 449e336903SWu, Josh csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */ 459e336903SWu, Josh /* Configure IO drive */ 46b899fa39SBo Shen csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 479e336903SWu, Josh 489e336903SWu, Josh writel(csa, &matrix->ebicsa); 499e336903SWu, Josh 509e336903SWu, Josh /* Configure SMC CS3 for NAND/SmartMedia */ 519e336903SWu, Josh writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 529e336903SWu, Josh AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 539e336903SWu, Josh &smc->cs[3].setup); 549e336903SWu, Josh writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 559e336903SWu, Josh AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 569e336903SWu, Josh &smc->cs[3].pulse); 579e336903SWu, Josh writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7), 589e336903SWu, Josh &smc->cs[3].cycle); 599e336903SWu, Josh writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 609e336903SWu, Josh AT91_SMC_MODE_EXNW_DISABLE | 619e336903SWu, Josh #ifdef CONFIG_SYS_NAND_DBW_16 629e336903SWu, Josh AT91_SMC_MODE_DBW_16 | 639e336903SWu, Josh #else /* CONFIG_SYS_NAND_DBW_8 */ 649e336903SWu, Josh AT91_SMC_MODE_DBW_8 | 659e336903SWu, Josh #endif 669e336903SWu, Josh AT91_SMC_MODE_TDF_CYCLE(1), 679e336903SWu, Josh &smc->cs[3].mode); 689e336903SWu, Josh 699e336903SWu, Josh /* Configure RDY/BSY pin */ 709e336903SWu, Josh at91_set_pio_input(AT91_PIO_PORTD, 5, 1); 719e336903SWu, Josh 729e336903SWu, Josh /* Configure ENABLE pin for NandFlash */ 739e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTD, 4, 1); 749e336903SWu, Josh 759e336903SWu, Josh at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 769e336903SWu, Josh at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 779e336903SWu, Josh at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ 789e336903SWu, Josh at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ 799e336903SWu, Josh } 809e336903SWu, Josh #endif 819e336903SWu, Josh 829e336903SWu, Josh #ifdef CONFIG_LCD 839e336903SWu, Josh vidinfo_t panel_info = { 849e336903SWu, Josh .vl_col = 480, 859e336903SWu, Josh .vl_row = 272, 869e336903SWu, Josh .vl_clk = 9000000, 879e336903SWu, Josh .vl_bpix = LCD_BPP, 889e336903SWu, Josh .vl_sync = 0, 899e336903SWu, Josh .vl_tft = 1, 909e336903SWu, Josh .vl_hsync_len = 5, 919e336903SWu, Josh .vl_left_margin = 8, 929e336903SWu, Josh .vl_right_margin = 43, 939e336903SWu, Josh .vl_vsync_len = 10, 949e336903SWu, Josh .vl_upper_margin = 4, 959e336903SWu, Josh .vl_lower_margin = 12, 969e336903SWu, Josh .mmio = ATMEL_BASE_LCDC, 979e336903SWu, Josh }; 989e336903SWu, Josh 999e336903SWu, Josh void lcd_enable(void) 1009e336903SWu, Josh { 1019e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ 1029e336903SWu, Josh } 1039e336903SWu, Josh 1049e336903SWu, Josh void lcd_disable(void) 1059e336903SWu, Josh { 1069e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */ 1079e336903SWu, Josh } 1089e336903SWu, Josh 1099e336903SWu, Josh #ifdef CONFIG_LCD_INFO 1109e336903SWu, Josh void lcd_show_board_info(void) 1119e336903SWu, Josh { 1129e336903SWu, Josh ulong dram_size, nand_size; 1139e336903SWu, Josh int i; 1149e336903SWu, Josh char temp[32]; 1159e336903SWu, Josh 1169e336903SWu, Josh lcd_printf("%s\n", U_BOOT_VERSION); 1179e336903SWu, Josh lcd_printf("ATMEL Corp\n"); 1189e336903SWu, Josh lcd_printf("at91@atmel.com\n"); 1199e336903SWu, Josh lcd_printf("%s CPU at %s MHz\n", 1209e336903SWu, Josh ATMEL_CPU_NAME, 1219e336903SWu, Josh strmhz(temp, get_cpu_clk_rate())); 1229e336903SWu, Josh 1239e336903SWu, Josh dram_size = 0; 1249e336903SWu, Josh for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 1259e336903SWu, Josh dram_size += gd->bd->bi_dram[i].size; 1269e336903SWu, Josh nand_size = 0; 1279e336903SWu, Josh for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 1289e336903SWu, Josh nand_size += nand_info[i].size; 1299e336903SWu, Josh lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 1309e336903SWu, Josh dram_size >> 20, 1319e336903SWu, Josh nand_size >> 20); 1329e336903SWu, Josh } 1339e336903SWu, Josh #endif /* CONFIG_LCD_INFO */ 1349e336903SWu, Josh #endif /* CONFIG_LCD */ 1359e336903SWu, Josh 1369e336903SWu, Josh /* SPI chip select control */ 1379e336903SWu, Josh #ifdef CONFIG_ATMEL_SPI 1389e336903SWu, Josh #include <spi.h> 1399e336903SWu, Josh int spi_cs_is_valid(unsigned int bus, unsigned int cs) 1409e336903SWu, Josh { 1419e336903SWu, Josh return bus == 0 && cs < 2; 1429e336903SWu, Josh } 1439e336903SWu, Josh 1449e336903SWu, Josh void spi_cs_activate(struct spi_slave *slave) 1459e336903SWu, Josh { 1469e336903SWu, Josh switch (slave->cs) { 1479e336903SWu, Josh case 0: 1489e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTA, 14, 0); 1499e336903SWu, Josh break; 1509e336903SWu, Josh case 1: 1519e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTA, 7, 0); 1529e336903SWu, Josh break; 1539e336903SWu, Josh } 1549e336903SWu, Josh } 1559e336903SWu, Josh 1569e336903SWu, Josh void spi_cs_deactivate(struct spi_slave *slave) 1579e336903SWu, Josh { 1589e336903SWu, Josh switch (slave->cs) { 1599e336903SWu, Josh case 0: 1609e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTA, 14, 1); 1619e336903SWu, Josh break; 1629e336903SWu, Josh case 1: 1639e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTA, 7, 1); 1649e336903SWu, Josh break; 1659e336903SWu, Josh } 1669e336903SWu, Josh } 1679e336903SWu, Josh #endif /* CONFIG_ATMEL_SPI */ 1689e336903SWu, Josh 1699e336903SWu, Josh #ifdef CONFIG_GENERIC_ATMEL_MCI 1709e336903SWu, Josh int board_mmc_init(bd_t *bd) 1719e336903SWu, Josh { 1729e336903SWu, Josh at91_mci_hw_init(); 1739e336903SWu, Josh 1749e336903SWu, Josh return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); 1759e336903SWu, Josh } 1769e336903SWu, Josh #endif 1779e336903SWu, Josh 17816276220SBo Shen #ifdef CONFIG_KS8851_MLL 17916276220SBo Shen void at91sam9n12ek_ks8851_hw_init(void) 18016276220SBo Shen { 18116276220SBo Shen struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 18216276220SBo Shen 18316276220SBo Shen writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 18416276220SBo Shen AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 18516276220SBo Shen &smc->cs[2].setup); 18616276220SBo Shen writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 18716276220SBo Shen AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), 18816276220SBo Shen &smc->cs[2].pulse); 18916276220SBo Shen writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), 19016276220SBo Shen &smc->cs[2].cycle); 19116276220SBo Shen writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 19216276220SBo Shen AT91_SMC_MODE_EXNW_DISABLE | 19316276220SBo Shen AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 19416276220SBo Shen AT91_SMC_MODE_TDF_CYCLE(1), 19516276220SBo Shen &smc->cs[2].mode); 19616276220SBo Shen 19716276220SBo Shen /* Configure NCS2 PIN */ 19816276220SBo Shen at91_set_b_periph(AT91_PIO_PORTD, 19, 0); 19916276220SBo Shen } 20016276220SBo Shen #endif 20116276220SBo Shen 202d9bef0adSBo Shen #ifdef CONFIG_USB_ATMEL 203d9bef0adSBo Shen void at91sam9n12ek_usb_hw_init(void) 204d9bef0adSBo Shen { 205d9bef0adSBo Shen at91_set_pio_output(AT91_PIO_PORTB, 7, 0); 206d9bef0adSBo Shen } 207d9bef0adSBo Shen #endif 208d9bef0adSBo Shen 2099e336903SWu, Josh int board_early_init_f(void) 2109e336903SWu, Josh { 2119e336903SWu, Josh /* Enable clocks for all PIOs */ 2129e336903SWu, Josh struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 2139e336903SWu, Josh writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer); 2149e336903SWu, Josh 2159e336903SWu, Josh at91_seriald_hw_init(); 2169e336903SWu, Josh return 0; 2179e336903SWu, Josh } 2189e336903SWu, Josh 2199e336903SWu, Josh int board_init(void) 2209e336903SWu, Josh { 2219e336903SWu, Josh /* adress of boot parameters */ 2229e336903SWu, Josh gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 2239e336903SWu, Josh 2249e336903SWu, Josh #ifdef CONFIG_NAND_ATMEL 2259e336903SWu, Josh at91sam9n12ek_nand_hw_init(); 2269e336903SWu, Josh #endif 2279e336903SWu, Josh 2289e336903SWu, Josh #ifdef CONFIG_ATMEL_SPI 2299e336903SWu, Josh at91_spi0_hw_init(1 << 0); 2309e336903SWu, Josh #endif 2319e336903SWu, Josh 2329e336903SWu, Josh #ifdef CONFIG_LCD 2339e336903SWu, Josh at91_lcd_hw_init(); 2349e336903SWu, Josh #endif 2359e336903SWu, Josh 23616276220SBo Shen #ifdef CONFIG_KS8851_MLL 23716276220SBo Shen at91sam9n12ek_ks8851_hw_init(); 23816276220SBo Shen #endif 23916276220SBo Shen 240d9bef0adSBo Shen #ifdef CONFIG_USB_ATMEL 241d9bef0adSBo Shen at91sam9n12ek_usb_hw_init(); 242d9bef0adSBo Shen #endif 243d9bef0adSBo Shen 2449e336903SWu, Josh return 0; 2459e336903SWu, Josh } 2469e336903SWu, Josh 24716276220SBo Shen #ifdef CONFIG_KS8851_MLL 24816276220SBo Shen int board_eth_init(bd_t *bis) 24916276220SBo Shen { 25016276220SBo Shen return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); 25116276220SBo Shen } 25216276220SBo Shen #endif 25316276220SBo Shen 2549e336903SWu, Josh int dram_init(void) 2559e336903SWu, Josh { 2569e336903SWu, Josh gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 2579e336903SWu, Josh CONFIG_SYS_SDRAM_SIZE); 2589e336903SWu, Josh return 0; 2599e336903SWu, Josh } 260*ff255e83SBo Shen 261*ff255e83SBo Shen #if defined(CONFIG_SPL_BUILD) 262*ff255e83SBo Shen #include <spl.h> 263*ff255e83SBo Shen #include <nand.h> 264*ff255e83SBo Shen 265*ff255e83SBo Shen void at91_spl_board_init(void) 266*ff255e83SBo Shen { 267*ff255e83SBo Shen #ifdef CONFIG_SYS_USE_MMC 268*ff255e83SBo Shen at91_mci_hw_init(); 269*ff255e83SBo Shen #elif CONFIG_SYS_USE_NANDFLASH 270*ff255e83SBo Shen at91sam9n12ek_nand_hw_init(); 271*ff255e83SBo Shen #elif CONFIG_SYS_USE_SPIFLASH 272*ff255e83SBo Shen at91_spi0_hw_init(1 << 4); 273*ff255e83SBo Shen #endif 274*ff255e83SBo Shen } 275*ff255e83SBo Shen 276*ff255e83SBo Shen #include <asm/arch/atmel_mpddrc.h> 277*ff255e83SBo Shen static void ddr2_conf(struct atmel_mpddr *ddr2) 278*ff255e83SBo Shen { 279*ff255e83SBo Shen ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 280*ff255e83SBo Shen 281*ff255e83SBo Shen ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 282*ff255e83SBo Shen ATMEL_MPDDRC_CR_NR_ROW_13 | 283*ff255e83SBo Shen ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 284*ff255e83SBo Shen ATMEL_MPDDRC_CR_NB_8BANKS | 285*ff255e83SBo Shen ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); 286*ff255e83SBo Shen 287*ff255e83SBo Shen ddr2->rtr = 0x411; 288*ff255e83SBo Shen 289*ff255e83SBo Shen ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 290*ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 291*ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 292*ff255e83SBo Shen 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 293*ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 294*ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 295*ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 296*ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 297*ff255e83SBo Shen 298*ff255e83SBo Shen ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 299*ff255e83SBo Shen 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 300*ff255e83SBo Shen 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 301*ff255e83SBo Shen 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 302*ff255e83SBo Shen 303*ff255e83SBo Shen ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 304*ff255e83SBo Shen 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 305*ff255e83SBo Shen 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 306*ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 307*ff255e83SBo Shen } 308*ff255e83SBo Shen 309*ff255e83SBo Shen void mem_init(void) 310*ff255e83SBo Shen { 311*ff255e83SBo Shen struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 312*ff255e83SBo Shen struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 313*ff255e83SBo Shen struct atmel_mpddr ddr2; 314*ff255e83SBo Shen unsigned long csa; 315*ff255e83SBo Shen 316*ff255e83SBo Shen ddr2_conf(&ddr2); 317*ff255e83SBo Shen 318*ff255e83SBo Shen /* enable DDR2 clock */ 319*ff255e83SBo Shen writel(0x4, &pmc->scer); 320*ff255e83SBo Shen 321*ff255e83SBo Shen /* Chip select 1 is for DDR2/SDRAM */ 322*ff255e83SBo Shen csa = readl(&matrix->ebicsa); 323*ff255e83SBo Shen csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 324*ff255e83SBo Shen csa &= ~AT91_MATRIX_EBI_DBPU_OFF; 325*ff255e83SBo Shen csa |= AT91_MATRIX_EBI_DBPD_OFF; 326*ff255e83SBo Shen csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 327*ff255e83SBo Shen writel(csa, &matrix->ebicsa); 328*ff255e83SBo Shen 329*ff255e83SBo Shen /* DDRAM2 Controller initialize */ 330*ff255e83SBo Shen ddr2_init(ATMEL_BASE_CS1, &ddr2); 331*ff255e83SBo Shen } 332*ff255e83SBo Shen #endif 333