19e336903SWu, Josh /* 29e336903SWu, Josh * (C) Copyright 2013 Atmel Corporation 39e336903SWu, Josh * Josh Wu <josh.wu@atmel.com> 49e336903SWu, Josh * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 69e336903SWu, Josh */ 79e336903SWu, Josh 89e336903SWu, Josh #include <common.h> 99e336903SWu, Josh #include <asm/io.h> 109e336903SWu, Josh #include <asm/arch/at91sam9x5_matrix.h> 119e336903SWu, Josh #include <asm/arch/at91sam9_smc.h> 129e336903SWu, Josh #include <asm/arch/at91_common.h> 139e336903SWu, Josh #include <asm/arch/at91_rstc.h> 149e336903SWu, Josh #include <asm/arch/at91_pio.h> 159e336903SWu, Josh #include <asm/arch/clk.h> 16c1868adfSWenyou Yang #include <debug_uart.h> 179e336903SWu, Josh #include <lcd.h> 189e336903SWu, Josh #include <atmel_hlcdc.h> 1916276220SBo Shen #include <netdev.h> 209e336903SWu, Josh 219e336903SWu, Josh #ifdef CONFIG_LCD_INFO 229e336903SWu, Josh #include <nand.h> 239e336903SWu, Josh #include <version.h> 249e336903SWu, Josh #endif 259e336903SWu, Josh 269e336903SWu, Josh DECLARE_GLOBAL_DATA_PTR; 279e336903SWu, Josh 289e336903SWu, Josh /* ------------------------------------------------------------------------- */ 299e336903SWu, Josh /* 309e336903SWu, Josh * Miscelaneous platform dependent initialisations 319e336903SWu, Josh */ 329e336903SWu, Josh #ifdef CONFIG_NAND_ATMEL 339e336903SWu, Josh static void at91sam9n12ek_nand_hw_init(void) 349e336903SWu, Josh { 359e336903SWu, Josh struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 369e336903SWu, Josh struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 379e336903SWu, Josh unsigned long csa; 389e336903SWu, Josh 399e336903SWu, Josh /* Assign CS3 to NAND/SmartMedia Interface */ 409e336903SWu, Josh csa = readl(&matrix->ebicsa); 419e336903SWu, Josh csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 429e336903SWu, Josh /* Configure databus */ 439e336903SWu, Josh csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */ 449e336903SWu, Josh /* Configure IO drive */ 45b899fa39SBo Shen csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 469e336903SWu, Josh 479e336903SWu, Josh writel(csa, &matrix->ebicsa); 489e336903SWu, Josh 499e336903SWu, Josh /* Configure SMC CS3 for NAND/SmartMedia */ 509e336903SWu, Josh writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 519e336903SWu, Josh AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), 529e336903SWu, Josh &smc->cs[3].setup); 539e336903SWu, Josh writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | 549e336903SWu, Josh AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), 559e336903SWu, Josh &smc->cs[3].pulse); 569e336903SWu, Josh writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7), 579e336903SWu, Josh &smc->cs[3].cycle); 589e336903SWu, Josh writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 599e336903SWu, Josh AT91_SMC_MODE_EXNW_DISABLE | 609e336903SWu, Josh #ifdef CONFIG_SYS_NAND_DBW_16 619e336903SWu, Josh AT91_SMC_MODE_DBW_16 | 629e336903SWu, Josh #else /* CONFIG_SYS_NAND_DBW_8 */ 639e336903SWu, Josh AT91_SMC_MODE_DBW_8 | 649e336903SWu, Josh #endif 659e336903SWu, Josh AT91_SMC_MODE_TDF_CYCLE(1), 669e336903SWu, Josh &smc->cs[3].mode); 679e336903SWu, Josh 689e336903SWu, Josh /* Configure RDY/BSY pin */ 699e336903SWu, Josh at91_set_pio_input(AT91_PIO_PORTD, 5, 1); 709e336903SWu, Josh 719e336903SWu, Josh /* Configure ENABLE pin for NandFlash */ 729e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTD, 4, 1); 739e336903SWu, Josh 742dc63f73SWenyou Yang at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ 752dc63f73SWenyou Yang at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ 762dc63f73SWenyou Yang at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ 772dc63f73SWenyou Yang at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ 789e336903SWu, Josh } 799e336903SWu, Josh #endif 809e336903SWu, Josh 819e336903SWu, Josh #ifdef CONFIG_LCD 829e336903SWu, Josh vidinfo_t panel_info = { 839e336903SWu, Josh .vl_col = 480, 849e336903SWu, Josh .vl_row = 272, 859e336903SWu, Josh .vl_clk = 9000000, 869e336903SWu, Josh .vl_bpix = LCD_BPP, 879e336903SWu, Josh .vl_sync = 0, 889e336903SWu, Josh .vl_tft = 1, 899e336903SWu, Josh .vl_hsync_len = 5, 909e336903SWu, Josh .vl_left_margin = 8, 919e336903SWu, Josh .vl_right_margin = 43, 929e336903SWu, Josh .vl_vsync_len = 10, 939e336903SWu, Josh .vl_upper_margin = 4, 949e336903SWu, Josh .vl_lower_margin = 12, 959e336903SWu, Josh .mmio = ATMEL_BASE_LCDC, 969e336903SWu, Josh }; 979e336903SWu, Josh 989e336903SWu, Josh void lcd_enable(void) 999e336903SWu, Josh { 1009e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ 1019e336903SWu, Josh } 1029e336903SWu, Josh 1039e336903SWu, Josh void lcd_disable(void) 1049e336903SWu, Josh { 1059e336903SWu, Josh at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */ 1069e336903SWu, Josh } 1079e336903SWu, Josh 1089e336903SWu, Josh #ifdef CONFIG_LCD_INFO 1099e336903SWu, Josh void lcd_show_board_info(void) 1109e336903SWu, Josh { 1119e336903SWu, Josh ulong dram_size, nand_size; 1129e336903SWu, Josh int i; 1139e336903SWu, Josh char temp[32]; 1149e336903SWu, Josh 1159e336903SWu, Josh lcd_printf("%s\n", U_BOOT_VERSION); 1169e336903SWu, Josh lcd_printf("ATMEL Corp\n"); 1179e336903SWu, Josh lcd_printf("at91@atmel.com\n"); 1189e336903SWu, Josh lcd_printf("%s CPU at %s MHz\n", 1199e336903SWu, Josh ATMEL_CPU_NAME, 1209e336903SWu, Josh strmhz(temp, get_cpu_clk_rate())); 1219e336903SWu, Josh 1229e336903SWu, Josh dram_size = 0; 1239e336903SWu, Josh for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 1249e336903SWu, Josh dram_size += gd->bd->bi_dram[i].size; 1259e336903SWu, Josh nand_size = 0; 1269e336903SWu, Josh for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 127*31f8d39eSGrygorii Strashko nand_size += get_nand_dev_by_index(i)->size; 1289e336903SWu, Josh lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", 1299e336903SWu, Josh dram_size >> 20, 1309e336903SWu, Josh nand_size >> 20); 1319e336903SWu, Josh } 1329e336903SWu, Josh #endif /* CONFIG_LCD_INFO */ 1339e336903SWu, Josh #endif /* CONFIG_LCD */ 1349e336903SWu, Josh 13516276220SBo Shen #ifdef CONFIG_KS8851_MLL 13616276220SBo Shen void at91sam9n12ek_ks8851_hw_init(void) 13716276220SBo Shen { 13816276220SBo Shen struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 13916276220SBo Shen 14016276220SBo Shen writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | 14116276220SBo Shen AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 14216276220SBo Shen &smc->cs[2].setup); 14316276220SBo Shen writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | 14416276220SBo Shen AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), 14516276220SBo Shen &smc->cs[2].pulse); 14616276220SBo Shen writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), 14716276220SBo Shen &smc->cs[2].cycle); 14816276220SBo Shen writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 14916276220SBo Shen AT91_SMC_MODE_EXNW_DISABLE | 15016276220SBo Shen AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | 15116276220SBo Shen AT91_SMC_MODE_TDF_CYCLE(1), 15216276220SBo Shen &smc->cs[2].mode); 15316276220SBo Shen 15416276220SBo Shen /* Configure NCS2 PIN */ 1552dc63f73SWenyou Yang at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0); 15616276220SBo Shen } 15716276220SBo Shen #endif 15816276220SBo Shen 159d9bef0adSBo Shen #ifdef CONFIG_USB_ATMEL 160d9bef0adSBo Shen void at91sam9n12ek_usb_hw_init(void) 161d9bef0adSBo Shen { 162d9bef0adSBo Shen at91_set_pio_output(AT91_PIO_PORTB, 7, 0); 163d9bef0adSBo Shen } 164d9bef0adSBo Shen #endif 165d9bef0adSBo Shen 166c1868adfSWenyou Yang #ifdef CONFIG_DEBUG_UART_BOARD_INIT 167c1868adfSWenyou Yang void board_debug_uart_init(void) 168c1868adfSWenyou Yang { 169c1868adfSWenyou Yang at91_seriald_hw_init(); 170c1868adfSWenyou Yang } 171c1868adfSWenyou Yang #endif 172c1868adfSWenyou Yang 173c1868adfSWenyou Yang #ifdef CONFIG_BOARD_EARLY_INIT_F 1749e336903SWu, Josh int board_early_init_f(void) 1759e336903SWu, Josh { 176c1868adfSWenyou Yang #ifdef CONFIG_DEBUG_UART 177c1868adfSWenyou Yang debug_uart_init(); 178c1868adfSWenyou Yang #endif 1799e336903SWu, Josh return 0; 1809e336903SWu, Josh } 181c1868adfSWenyou Yang #endif 1829e336903SWu, Josh 1839e336903SWu, Josh int board_init(void) 1849e336903SWu, Josh { 1859e336903SWu, Josh /* adress of boot parameters */ 1869e336903SWu, Josh gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 1879e336903SWu, Josh 1889e336903SWu, Josh #ifdef CONFIG_NAND_ATMEL 1899e336903SWu, Josh at91sam9n12ek_nand_hw_init(); 1909e336903SWu, Josh #endif 1919e336903SWu, Josh 1929e336903SWu, Josh #ifdef CONFIG_LCD 1939e336903SWu, Josh at91_lcd_hw_init(); 1949e336903SWu, Josh #endif 1959e336903SWu, Josh 19616276220SBo Shen #ifdef CONFIG_KS8851_MLL 19716276220SBo Shen at91sam9n12ek_ks8851_hw_init(); 19816276220SBo Shen #endif 19916276220SBo Shen 200d9bef0adSBo Shen #ifdef CONFIG_USB_ATMEL 201d9bef0adSBo Shen at91sam9n12ek_usb_hw_init(); 202d9bef0adSBo Shen #endif 203d9bef0adSBo Shen 2049e336903SWu, Josh return 0; 2059e336903SWu, Josh } 2069e336903SWu, Josh 20716276220SBo Shen #ifdef CONFIG_KS8851_MLL 20816276220SBo Shen int board_eth_init(bd_t *bis) 20916276220SBo Shen { 21016276220SBo Shen return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); 21116276220SBo Shen } 21216276220SBo Shen #endif 21316276220SBo Shen 2149e336903SWu, Josh int dram_init(void) 2159e336903SWu, Josh { 2169e336903SWu, Josh gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 2179e336903SWu, Josh CONFIG_SYS_SDRAM_SIZE); 2189e336903SWu, Josh return 0; 2199e336903SWu, Josh } 220ff255e83SBo Shen 221ff255e83SBo Shen #if defined(CONFIG_SPL_BUILD) 222ff255e83SBo Shen #include <spl.h> 223ff255e83SBo Shen #include <nand.h> 224ff255e83SBo Shen 225ff255e83SBo Shen void at91_spl_board_init(void) 226ff255e83SBo Shen { 227ff255e83SBo Shen #ifdef CONFIG_SYS_USE_MMC 228ff255e83SBo Shen at91_mci_hw_init(); 229ff255e83SBo Shen #elif CONFIG_SYS_USE_NANDFLASH 230ff255e83SBo Shen at91sam9n12ek_nand_hw_init(); 231ff255e83SBo Shen #elif CONFIG_SYS_USE_SPIFLASH 232ff255e83SBo Shen at91_spi0_hw_init(1 << 4); 233ff255e83SBo Shen #endif 234ff255e83SBo Shen } 235ff255e83SBo Shen 236ff255e83SBo Shen #include <asm/arch/atmel_mpddrc.h> 2377e8702a0SWenyou Yang static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 238ff255e83SBo Shen { 239ff255e83SBo Shen ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 240ff255e83SBo Shen 241ff255e83SBo Shen ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 242ff255e83SBo Shen ATMEL_MPDDRC_CR_NR_ROW_13 | 243ff255e83SBo Shen ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 244ff255e83SBo Shen ATMEL_MPDDRC_CR_NB_8BANKS | 245ff255e83SBo Shen ATMEL_MPDDRC_CR_DECOD_INTERLEAVED); 246ff255e83SBo Shen 247ff255e83SBo Shen ddr2->rtr = 0x411; 248ff255e83SBo Shen 249ff255e83SBo Shen ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 250ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 251ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 252ff255e83SBo Shen 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 253ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 254ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 255ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 256ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 257ff255e83SBo Shen 258ff255e83SBo Shen ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 259ff255e83SBo Shen 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 260ff255e83SBo Shen 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 261ff255e83SBo Shen 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 262ff255e83SBo Shen 263ff255e83SBo Shen ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 264ff255e83SBo Shen 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 265ff255e83SBo Shen 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 266ff255e83SBo Shen 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 267ff255e83SBo Shen } 268ff255e83SBo Shen 269ff255e83SBo Shen void mem_init(void) 270ff255e83SBo Shen { 271ff255e83SBo Shen struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 272ff255e83SBo Shen struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 2737e8702a0SWenyou Yang struct atmel_mpddrc_config ddr2; 274ff255e83SBo Shen unsigned long csa; 275ff255e83SBo Shen 276ff255e83SBo Shen ddr2_conf(&ddr2); 277ff255e83SBo Shen 278ff255e83SBo Shen /* enable DDR2 clock */ 279c982f6b9SErik van Luijk writel(AT91_PMC_DDR, &pmc->scer); 280ff255e83SBo Shen 281ff255e83SBo Shen /* Chip select 1 is for DDR2/SDRAM */ 282ff255e83SBo Shen csa = readl(&matrix->ebicsa); 283ff255e83SBo Shen csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; 284ff255e83SBo Shen csa &= ~AT91_MATRIX_EBI_DBPU_OFF; 285ff255e83SBo Shen csa |= AT91_MATRIX_EBI_DBPD_OFF; 286ff255e83SBo Shen csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; 287ff255e83SBo Shen writel(csa, &matrix->ebicsa); 288ff255e83SBo Shen 289ff255e83SBo Shen /* DDRAM2 Controller initialize */ 2900c01c3e8SErik van Luijk ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); 291ff255e83SBo Shen } 292ff255e83SBo Shen #endif 293