1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clk.h> 12 #include <asm/arch/at91sam9g45_matrix.h> 13 #include <asm/arch/at91sam9_smc.h> 14 #include <asm/arch/at91_common.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <lcd.h> 18 #include <linux/mtd/nand.h> 19 #include <atmel_lcdc.h> 20 #include <atmel_mci.h> 21 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 22 #include <net.h> 23 #endif 24 #include <netdev.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 /* ------------------------------------------------------------------------- */ 29 /* 30 * Miscelaneous platform dependent initialisations 31 */ 32 33 #ifdef CONFIG_CMD_NAND 34 void at91sam9m10g45ek_nand_hw_init(void) 35 { 36 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 38 unsigned long csa; 39 40 /* Enable CS3 */ 41 csa = readl(&matrix->ebicsa); 42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 43 writel(csa, &matrix->ebicsa); 44 45 /* Configure SMC CS3 for NAND/SmartMedia */ 46 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 48 &smc->cs[3].setup); 49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | 50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), 51 &smc->cs[3].pulse); 52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), 53 &smc->cs[3].cycle); 54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 55 AT91_SMC_MODE_EXNW_DISABLE | 56 #ifdef CONFIG_SYS_NAND_DBW_16 57 AT91_SMC_MODE_DBW_16 | 58 #else /* CONFIG_SYS_NAND_DBW_8 */ 59 AT91_SMC_MODE_DBW_8 | 60 #endif 61 AT91_SMC_MODE_TDF_CYCLE(3), 62 &smc->cs[3].mode); 63 64 at91_periph_clk_enable(ATMEL_ID_PIOC); 65 66 /* Configure RDY/BSY */ 67 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 68 69 /* Enable NandFlash */ 70 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 71 } 72 #endif 73 74 #if defined(CONFIG_SPL_BUILD) 75 #include <spl.h> 76 #include <nand.h> 77 78 void at91_spl_board_init(void) 79 { 80 /* 81 * On the at91sam9m10g45ek board, the chip wm9711 stays in the 82 * test mode, so it needs do some action to exit test mode. 83 */ 84 at91_periph_clk_enable(ATMEL_ID_PIODE); 85 at91_set_gpio_output(AT91_PIN_PD7, 0); 86 at91_set_gpio_output(AT91_PIN_PD8, 0); 87 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); 88 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); 89 90 #ifdef CONFIG_SYS_USE_MMC 91 at91_mci_hw_init(); 92 #elif CONFIG_SYS_USE_NANDFLASH 93 at91sam9m10g45ek_nand_hw_init(); 94 #endif 95 } 96 97 #include <asm/arch/atmel_mpddrc.h> 98 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 99 { 100 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 101 102 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 103 ATMEL_MPDDRC_CR_NR_ROW_14 | 104 ATMEL_MPDDRC_CR_DQMS_SHARED | 105 ATMEL_MPDDRC_CR_CAS_DDR_CAS3); 106 107 ddr2->rtr = 0x24b; 108 109 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 110 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ 111 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ 112 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ 113 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ 114 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ 115 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ 116 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ 117 118 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 119 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 120 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 121 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 122 123 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 124 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 125 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 126 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 127 } 128 129 void mem_init(void) 130 { 131 struct atmel_mpddrc_config ddr2; 132 133 ddr2_conf(&ddr2); 134 135 at91_system_clk_enable(AT91_PMC_DDR); 136 137 /* DDRAM2 Controller initialize */ 138 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); 139 } 140 #endif 141 142 #ifdef CONFIG_CMD_USB 143 static void at91sam9m10g45ek_usb_hw_init(void) 144 { 145 at91_periph_clk_enable(ATMEL_ID_PIODE); 146 147 at91_set_gpio_output(AT91_PIN_PD1, 0); 148 at91_set_gpio_output(AT91_PIN_PD3, 0); 149 } 150 #endif 151 152 #ifdef CONFIG_MACB 153 static void at91sam9m10g45ek_macb_hw_init(void) 154 { 155 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 156 157 at91_periph_clk_enable(ATMEL_ID_EMAC); 158 159 /* 160 * Disable pull-up on: 161 * RXDV (PA15) => PHY normal mode (not Test mode) 162 * ERX0 (PA12) => PHY ADDR0 163 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 164 * 165 * PHY has internal pull-down 166 */ 167 writel(pin_to_mask(AT91_PIN_PA15) | 168 pin_to_mask(AT91_PIN_PA12) | 169 pin_to_mask(AT91_PIN_PA13), 170 &pioa->pudr); 171 172 at91_phy_reset(); 173 174 /* Re-enable pull-up */ 175 writel(pin_to_mask(AT91_PIN_PA15) | 176 pin_to_mask(AT91_PIN_PA12) | 177 pin_to_mask(AT91_PIN_PA13), 178 &pioa->puer); 179 180 /* And the pins. */ 181 at91_macb_hw_init(); 182 } 183 #endif 184 185 #ifdef CONFIG_LCD 186 187 vidinfo_t panel_info = { 188 .vl_col = 480, 189 .vl_row = 272, 190 .vl_clk = 9000000, 191 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | 192 ATMEL_LCDC_INVFRAME_NORMAL, 193 .vl_bpix = 3, 194 .vl_tft = 1, 195 .vl_hsync_len = 45, 196 .vl_left_margin = 1, 197 .vl_right_margin = 1, 198 .vl_vsync_len = 1, 199 .vl_upper_margin = 40, 200 .vl_lower_margin = 1, 201 .mmio = ATMEL_BASE_LCDC, 202 }; 203 204 205 void lcd_enable(void) 206 { 207 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ 208 } 209 210 void lcd_disable(void) 211 { 212 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ 213 } 214 215 static void at91sam9m10g45ek_lcd_hw_init(void) 216 { 217 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ 218 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ 219 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ 220 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ 221 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ 222 223 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ 224 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ 225 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ 226 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ 227 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ 228 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ 229 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ 230 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ 231 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ 232 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ 233 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ 234 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ 235 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ 236 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ 237 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ 238 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ 239 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ 240 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ 241 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ 242 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ 243 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ 244 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ 245 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ 246 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ 247 248 at91_periph_clk_enable(ATMEL_ID_LCDC); 249 250 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; 251 } 252 253 #ifdef CONFIG_LCD_INFO 254 #include <nand.h> 255 #include <version.h> 256 257 void lcd_show_board_info(void) 258 { 259 ulong dram_size, nand_size; 260 int i; 261 char temp[32]; 262 263 lcd_printf ("%s\n", U_BOOT_VERSION); 264 lcd_printf ("(C) 2008 ATMEL Corp\n"); 265 lcd_printf ("at91support@atmel.com\n"); 266 lcd_printf ("%s CPU at %s MHz\n", 267 ATMEL_CPU_NAME, 268 strmhz(temp, get_cpu_clk_rate())); 269 270 dram_size = 0; 271 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 272 dram_size += gd->bd->bi_dram[i].size; 273 nand_size = 0; 274 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 275 nand_size += nand_info[i]->size; 276 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 277 dram_size >> 20, 278 nand_size >> 20 ); 279 } 280 #endif /* CONFIG_LCD_INFO */ 281 #endif 282 283 #ifdef CONFIG_GENERIC_ATMEL_MCI 284 int board_mmc_init(bd_t *bis) 285 { 286 at91_mci_hw_init(); 287 288 return atmel_mci_init((void *)ATMEL_BASE_MCI0); 289 } 290 #endif 291 292 int board_early_init_f(void) 293 { 294 at91_seriald_hw_init(); 295 return 0; 296 } 297 298 int board_init(void) 299 { 300 /* arch number of AT91SAM9M10G45EK-Board */ 301 #ifdef CONFIG_AT91SAM9M10G45EK 302 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; 303 #elif defined CONFIG_AT91SAM9G45EKES 304 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; 305 #endif 306 307 /* adress of boot parameters */ 308 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 309 310 #ifdef CONFIG_CMD_NAND 311 at91sam9m10g45ek_nand_hw_init(); 312 #endif 313 #ifdef CONFIG_CMD_USB 314 at91sam9m10g45ek_usb_hw_init(); 315 #endif 316 #ifdef CONFIG_HAS_DATAFLASH 317 at91_spi0_hw_init(1 << 0); 318 #endif 319 #ifdef CONFIG_ATMEL_SPI 320 at91_spi0_hw_init(1 << 4); 321 #endif 322 #ifdef CONFIG_MACB 323 at91sam9m10g45ek_macb_hw_init(); 324 #endif 325 #ifdef CONFIG_LCD 326 at91sam9m10g45ek_lcd_hw_init(); 327 #endif 328 return 0; 329 } 330 331 int dram_init(void) 332 { 333 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 334 CONFIG_SYS_SDRAM_SIZE); 335 return 0; 336 } 337 338 #ifdef CONFIG_RESET_PHY_R 339 void reset_phy(void) 340 { 341 } 342 #endif 343 344 int board_eth_init(bd_t *bis) 345 { 346 int rc = 0; 347 #ifdef CONFIG_MACB 348 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 349 #endif 350 return rc; 351 } 352 353 /* SPI chip select control */ 354 #ifdef CONFIG_ATMEL_SPI 355 #include <spi.h> 356 357 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 358 { 359 return bus == 0 && cs < 2; 360 } 361 362 void spi_cs_activate(struct spi_slave *slave) 363 { 364 switch(slave->cs) { 365 case 1: 366 at91_set_gpio_output(AT91_PIN_PB18, 0); 367 break; 368 case 0: 369 default: 370 at91_set_gpio_output(AT91_PIN_PB3, 0); 371 break; 372 } 373 } 374 375 void spi_cs_deactivate(struct spi_slave *slave) 376 { 377 switch(slave->cs) { 378 case 1: 379 at91_set_gpio_output(AT91_PIN_PB18, 1); 380 break; 381 case 0: 382 default: 383 at91_set_gpio_output(AT91_PIN_PB3, 1); 384 break; 385 } 386 } 387 #endif /* CONFIG_ATMEL_SPI */ 388