1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/at91sam9g45_matrix.h>
13 #include <asm/arch/at91sam9_smc.h>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91_pmc.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/clk.h>
18 #include <lcd.h>
19 #include <linux/mtd/nand.h>
20 #include <atmel_lcdc.h>
21 #include <atmel_mci.h>
22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
23 #include <net.h>
24 #endif
25 #include <netdev.h>
26 
27 DECLARE_GLOBAL_DATA_PTR;
28 
29 /* ------------------------------------------------------------------------- */
30 /*
31  * Miscelaneous platform dependent initialisations
32  */
33 
34 #ifdef CONFIG_CMD_NAND
35 void at91sam9m10g45ek_nand_hw_init(void)
36 {
37 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
38 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
39 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
40 	unsigned long csa;
41 
42 	/* Enable CS3 */
43 	csa = readl(&matrix->ebicsa);
44 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
45 	writel(csa, &matrix->ebicsa);
46 
47 	/* Configure SMC CS3 for NAND/SmartMedia */
48 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
49 	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 	       &smc->cs[3].setup);
51 	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
52 	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
53 	       &smc->cs[3].pulse);
54 	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
55 	       &smc->cs[3].cycle);
56 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
57 	       AT91_SMC_MODE_EXNW_DISABLE |
58 #ifdef CONFIG_SYS_NAND_DBW_16
59 	       AT91_SMC_MODE_DBW_16 |
60 #else /* CONFIG_SYS_NAND_DBW_8 */
61 	       AT91_SMC_MODE_DBW_8 |
62 #endif
63 	       AT91_SMC_MODE_TDF_CYCLE(3),
64 	       &smc->cs[3].mode);
65 
66 	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
67 
68 	/* Configure RDY/BSY */
69 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
70 
71 	/* Enable NandFlash */
72 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
73 }
74 #endif
75 
76 #if defined(CONFIG_SPL_BUILD)
77 #include <spl.h>
78 #include <nand.h>
79 
80 void at91_spl_board_init(void)
81 {
82 	/*
83 	 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
84 	 * test mode, so it needs do some action to exit test mode.
85 	 */
86 	at91_periph_clk_enable(ATMEL_ID_PIODE);
87 	at91_set_gpio_output(AT91_PIN_PD7, 0);
88 	at91_set_gpio_output(AT91_PIN_PD8, 0);
89 	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
90 	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
91 
92 #ifdef CONFIG_SYS_USE_MMC
93 	at91_mci_hw_init();
94 #elif CONFIG_SYS_USE_NANDFLASH
95 	at91sam9m10g45ek_nand_hw_init();
96 #endif
97 }
98 
99 #include <asm/arch/atmel_mpddrc.h>
100 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
101 {
102 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
103 
104 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
105 		    ATMEL_MPDDRC_CR_NR_ROW_14 |
106 		    ATMEL_MPDDRC_CR_DQMS_SHARED |
107 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
108 
109 	ddr2->rtr = 0x24b;
110 
111 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
112 		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
113 		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
114 		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
115 		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
116 		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
117 		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
118 		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
119 
120 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
121 		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
122 		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
123 		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
124 
125 	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
126 		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
127 		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
128 		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
129 }
130 
131 void mem_init(void)
132 {
133 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
134 	struct atmel_mpddrc_config ddr2;
135 
136 	ddr2_conf(&ddr2);
137 
138 	/* enable DDR2 clock */
139 	writel(AT91_PMC_DDR, &pmc->scer);
140 
141 	/* DDRAM2 Controller initialize */
142 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
143 }
144 #endif
145 
146 #ifdef CONFIG_CMD_USB
147 static void at91sam9m10g45ek_usb_hw_init(void)
148 {
149 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
150 
151 	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
152 
153 	at91_set_gpio_output(AT91_PIN_PD1, 0);
154 	at91_set_gpio_output(AT91_PIN_PD3, 0);
155 }
156 #endif
157 
158 #ifdef CONFIG_MACB
159 static void at91sam9m10g45ek_macb_hw_init(void)
160 {
161 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
162 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
163 
164 	/* Enable clock */
165 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
166 
167 	/*
168 	 * Disable pull-up on:
169 	 *      RXDV (PA15) => PHY normal mode (not Test mode)
170 	 *      ERX0 (PA12) => PHY ADDR0
171 	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
172 	 *
173 	 * PHY has internal pull-down
174 	 */
175 	writel(pin_to_mask(AT91_PIN_PA15) |
176 	       pin_to_mask(AT91_PIN_PA12) |
177 	       pin_to_mask(AT91_PIN_PA13),
178 	       &pioa->pudr);
179 
180 	at91_phy_reset();
181 
182 	/* Re-enable pull-up */
183 	writel(pin_to_mask(AT91_PIN_PA15) |
184 	       pin_to_mask(AT91_PIN_PA12) |
185 	       pin_to_mask(AT91_PIN_PA13),
186 	       &pioa->puer);
187 
188 	/* And the pins. */
189 	at91_macb_hw_init();
190 }
191 #endif
192 
193 #ifdef CONFIG_LCD
194 
195 vidinfo_t panel_info = {
196 	.vl_col =		480,
197 	.vl_row =		272,
198 	.vl_clk =		9000000,
199 	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
200 				ATMEL_LCDC_INVFRAME_NORMAL,
201 	.vl_bpix =		3,
202 	.vl_tft =		1,
203 	.vl_hsync_len =		45,
204 	.vl_left_margin =	1,
205 	.vl_right_margin =	1,
206 	.vl_vsync_len =		1,
207 	.vl_upper_margin =	40,
208 	.vl_lower_margin =	1,
209 	.mmio =			ATMEL_BASE_LCDC,
210 };
211 
212 
213 void lcd_enable(void)
214 {
215 	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
216 }
217 
218 void lcd_disable(void)
219 {
220 	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
221 }
222 
223 static void at91sam9m10g45ek_lcd_hw_init(void)
224 {
225 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
226 
227 	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
228 	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
229 	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
230 	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
231 	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
232 
233 	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
234 	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
235 	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
236 	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
237 	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
238 	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
239 	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
240 	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
241 	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
242 	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
243 	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
244 	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
245 	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
246 	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
247 	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
248 	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
249 	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
250 	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
251 	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
252 	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
253 	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
254 	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
255 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
256 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
257 
258 	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
259 
260 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
261 }
262 
263 #ifdef CONFIG_LCD_INFO
264 #include <nand.h>
265 #include <version.h>
266 
267 void lcd_show_board_info(void)
268 {
269 	ulong dram_size, nand_size;
270 	int i;
271 	char temp[32];
272 
273 	lcd_printf ("%s\n", U_BOOT_VERSION);
274 	lcd_printf ("(C) 2008 ATMEL Corp\n");
275 	lcd_printf ("at91support@atmel.com\n");
276 	lcd_printf ("%s CPU at %s MHz\n",
277 		ATMEL_CPU_NAME,
278 		strmhz(temp, get_cpu_clk_rate()));
279 
280 	dram_size = 0;
281 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
282 		dram_size += gd->bd->bi_dram[i].size;
283 	nand_size = 0;
284 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
285 		nand_size += nand_info[i].size;
286 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
287 		dram_size >> 20,
288 		nand_size >> 20 );
289 }
290 #endif /* CONFIG_LCD_INFO */
291 #endif
292 
293 #ifdef CONFIG_GENERIC_ATMEL_MCI
294 int board_mmc_init(bd_t *bis)
295 {
296 	at91_mci_hw_init();
297 
298 	return atmel_mci_init((void *)ATMEL_BASE_MCI0);
299 }
300 #endif
301 
302 int board_early_init_f(void)
303 {
304 	at91_seriald_hw_init();
305 	return 0;
306 }
307 
308 int board_init(void)
309 {
310 	/* arch number of AT91SAM9M10G45EK-Board */
311 #ifdef CONFIG_AT91SAM9M10G45EK
312 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
313 #elif defined CONFIG_AT91SAM9G45EKES
314 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
315 #endif
316 
317 	/* adress of boot parameters */
318 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
319 
320 #ifdef CONFIG_CMD_NAND
321 	at91sam9m10g45ek_nand_hw_init();
322 #endif
323 #ifdef CONFIG_CMD_USB
324 	at91sam9m10g45ek_usb_hw_init();
325 #endif
326 #ifdef CONFIG_HAS_DATAFLASH
327 	at91_spi0_hw_init(1 << 0);
328 #endif
329 #ifdef CONFIG_ATMEL_SPI
330 	at91_spi0_hw_init(1 << 4);
331 #endif
332 #ifdef CONFIG_MACB
333 	at91sam9m10g45ek_macb_hw_init();
334 #endif
335 #ifdef CONFIG_LCD
336 	at91sam9m10g45ek_lcd_hw_init();
337 #endif
338 	return 0;
339 }
340 
341 int dram_init(void)
342 {
343 	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
344 				    CONFIG_SYS_SDRAM_SIZE);
345 	return 0;
346 }
347 
348 #ifdef CONFIG_RESET_PHY_R
349 void reset_phy(void)
350 {
351 }
352 #endif
353 
354 int board_eth_init(bd_t *bis)
355 {
356 	int rc = 0;
357 #ifdef CONFIG_MACB
358 	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
359 #endif
360 	return rc;
361 }
362 
363 /* SPI chip select control */
364 #ifdef CONFIG_ATMEL_SPI
365 #include <spi.h>
366 
367 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
368 {
369 	return bus == 0 && cs < 2;
370 }
371 
372 void spi_cs_activate(struct spi_slave *slave)
373 {
374 	switch(slave->cs) {
375 		case 1:
376 			at91_set_gpio_output(AT91_PIN_PB18, 0);
377 			break;
378 		case 0:
379 		default:
380 			at91_set_gpio_output(AT91_PIN_PB3, 0);
381 			break;
382 	}
383 }
384 
385 void spi_cs_deactivate(struct spi_slave *slave)
386 {
387 	switch(slave->cs) {
388 		case 1:
389 			at91_set_gpio_output(AT91_PIN_PB18, 1);
390 			break;
391 		case 0:
392 		default:
393 			at91_set_gpio_output(AT91_PIN_PB3, 1);
394 		break;
395 	}
396 }
397 #endif /* CONFIG_ATMEL_SPI */
398