1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <asm/io.h>
27 #include <asm/arch/at91sam9g45_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_common.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/clk.h>
34 #include <lcd.h>
35 #include <atmel_lcdc.h>
36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
37 #include <net.h>
38 #endif
39 #include <netdev.h>
40 
41 DECLARE_GLOBAL_DATA_PTR;
42 
43 /* ------------------------------------------------------------------------- */
44 /*
45  * Miscelaneous platform dependent initialisations
46  */
47 
48 #ifdef CONFIG_CMD_NAND
49 void at91sam9m10g45ek_nand_hw_init(void)
50 {
51 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
52 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
53 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
54 	unsigned long csa;
55 
56 	/* Enable CS3 */
57 	csa = readl(&matrix->ebicsa);
58 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
59 	writel(csa, &matrix->ebicsa);
60 
61 	/* Configure SMC CS3 for NAND/SmartMedia */
62 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
63 	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
64 	       &smc->cs[3].setup);
65 	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
66 	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
67 	       &smc->cs[3].pulse);
68 	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
69 	       &smc->cs[3].cycle);
70 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
71 	       AT91_SMC_MODE_EXNW_DISABLE |
72 #ifdef CONFIG_SYS_NAND_DBW_16
73 	       AT91_SMC_MODE_DBW_16 |
74 #else /* CONFIG_SYS_NAND_DBW_8 */
75 	       AT91_SMC_MODE_DBW_8 |
76 #endif
77 	       AT91_SMC_MODE_TDF_CYCLE(3),
78 	       &smc->cs[3].mode);
79 
80 	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
81 
82 	/* Configure RDY/BSY */
83 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
84 
85 	/* Enable NandFlash */
86 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
87 }
88 #endif
89 
90 #ifdef CONFIG_CMD_USB
91 static void at91sam9m10g45ek_usb_hw_init(void)
92 {
93 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
94 
95 	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
96 
97 	at91_set_gpio_output(AT91_PIN_PD1, 0);
98 	at91_set_gpio_output(AT91_PIN_PD3, 0);
99 }
100 #endif
101 
102 #ifdef CONFIG_MACB
103 static void at91sam9m10g45ek_macb_hw_init(void)
104 {
105 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
106 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
107 	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
108 	unsigned long erstl;
109 
110 	/* Enable clock */
111 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
112 
113 	/*
114 	 * Disable pull-up on:
115 	 *      RXDV (PA15) => PHY normal mode (not Test mode)
116 	 *      ERX0 (PA12) => PHY ADDR0
117 	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
118 	 *
119 	 * PHY has internal pull-down
120 	 */
121 	writel(pin_to_mask(AT91_PIN_PA15) |
122 	       pin_to_mask(AT91_PIN_PA12) |
123 	       pin_to_mask(AT91_PIN_PA13),
124 	       &pioa->pudr);
125 
126 	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
127 
128 	/* Need to reset PHY -> 500ms reset */
129 	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
130 		AT91_RSTC_MR_URSTEN, &rstc->mr);
131 
132 	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
133 
134 	/* Wait for end hardware reset */
135 	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
136 		;
137 
138 	/* Restore NRST value */
139 	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
140 		&rstc->mr);
141 
142 	/* Re-enable pull-up */
143 	writel(pin_to_mask(AT91_PIN_PA15) |
144 	       pin_to_mask(AT91_PIN_PA12) |
145 	       pin_to_mask(AT91_PIN_PA13),
146 	       &pioa->puer);
147 
148 	/* And the pins. */
149 	at91_macb_hw_init();
150 }
151 #endif
152 
153 #ifdef CONFIG_LCD
154 
155 vidinfo_t panel_info = {
156 	vl_col:		480,
157 	vl_row:		272,
158 	vl_clk:		9000000,
159 	vl_sync:	ATMEL_LCDC_INVLINE_NORMAL |
160 			ATMEL_LCDC_INVFRAME_NORMAL,
161 	vl_bpix:	3,
162 	vl_tft:		1,
163 	vl_hsync_len:	45,
164 	vl_left_margin:	1,
165 	vl_right_margin:1,
166 	vl_vsync_len:	1,
167 	vl_upper_margin:40,
168 	vl_lower_margin:1,
169 	mmio :		 ATMEL_BASE_LCDC,
170 };
171 
172 
173 void lcd_enable(void)
174 {
175 	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
176 }
177 
178 void lcd_disable(void)
179 {
180 	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
181 }
182 
183 static void at91sam9m10g45ek_lcd_hw_init(void)
184 {
185 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
186 
187 	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
188 	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
189 	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
190 	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
191 	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
192 
193 	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
194 	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
195 	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
196 	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
197 	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
198 	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
199 	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
200 	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
201 	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
202 	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
203 	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
204 	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
205 	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
206 	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
207 	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
208 	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
209 	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
210 	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
211 	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
212 	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
213 	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
214 	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
215 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
216 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
217 
218 	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
219 
220 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
221 }
222 
223 #ifdef CONFIG_LCD_INFO
224 #include <nand.h>
225 #include <version.h>
226 
227 void lcd_show_board_info(void)
228 {
229 	ulong dram_size, nand_size;
230 	int i;
231 	char temp[32];
232 
233 	lcd_printf ("%s\n", U_BOOT_VERSION);
234 	lcd_printf ("(C) 2008 ATMEL Corp\n");
235 	lcd_printf ("at91support@atmel.com\n");
236 	lcd_printf ("%s CPU at %s MHz\n",
237 		ATMEL_CPU_NAME,
238 		strmhz(temp, get_cpu_clk_rate()));
239 
240 	dram_size = 0;
241 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
242 		dram_size += gd->bd->bi_dram[i].size;
243 	nand_size = 0;
244 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
245 		nand_size += nand_info[i].size;
246 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
247 		dram_size >> 20,
248 		nand_size >> 20 );
249 }
250 #endif /* CONFIG_LCD_INFO */
251 #endif
252 
253 int board_early_init_f(void)
254 {
255 	at91_seriald_hw_init();
256 	return 0;
257 }
258 
259 int board_init(void)
260 {
261 	/* arch number of AT91SAM9M10G45EK-Board */
262 #ifdef CONFIG_AT91SAM9M10G45EK
263 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
264 #elif defined CONFIG_AT91SAM9G45EKES
265 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
266 #endif
267 
268 	/* adress of boot parameters */
269 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
270 
271 #ifdef CONFIG_CMD_NAND
272 	at91sam9m10g45ek_nand_hw_init();
273 #endif
274 #ifdef CONFIG_CMD_USB
275 	at91sam9m10g45ek_usb_hw_init();
276 #endif
277 #ifdef CONFIG_HAS_DATAFLASH
278 	at91_spi0_hw_init(1 << 0);
279 #endif
280 #ifdef CONFIG_ATMEL_SPI
281 	at91_spi0_hw_init(1 << 4);
282 #endif
283 #ifdef CONFIG_MACB
284 	at91sam9m10g45ek_macb_hw_init();
285 #endif
286 #ifdef CONFIG_LCD
287 	at91sam9m10g45ek_lcd_hw_init();
288 #endif
289 	return 0;
290 }
291 
292 int dram_init(void)
293 {
294 	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
295 				    CONFIG_SYS_SDRAM_SIZE);
296 	return 0;
297 }
298 
299 #ifdef CONFIG_RESET_PHY_R
300 void reset_phy(void)
301 {
302 }
303 #endif
304 
305 int board_eth_init(bd_t *bis)
306 {
307 	int rc = 0;
308 #ifdef CONFIG_MACB
309 	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
310 #endif
311 	return rc;
312 }
313 
314 /* SPI chip select control */
315 #ifdef CONFIG_ATMEL_SPI
316 #include <spi.h>
317 
318 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
319 {
320 	return bus == 0 && cs < 2;
321 }
322 
323 void spi_cs_activate(struct spi_slave *slave)
324 {
325 	switch(slave->cs) {
326 		case 1:
327 			at91_set_gpio_output(AT91_PIN_PB18, 0);
328 			break;
329 		case 0:
330 		default:
331 			at91_set_gpio_output(AT91_PIN_PB3, 0);
332 			break;
333 	}
334 }
335 
336 void spi_cs_deactivate(struct spi_slave *slave)
337 {
338 	switch(slave->cs) {
339 		case 1:
340 			at91_set_gpio_output(AT91_PIN_PB18, 1);
341 			break;
342 		case 0:
343 		default:
344 			at91_set_gpio_output(AT91_PIN_PB3, 1);
345 		break;
346 	}
347 }
348 #endif /* CONFIG_ATMEL_SPI */
349