1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <debug_uart.h>
11 #include <asm/io.h>
12 #include <asm/arch/clk.h>
13 #include <asm/arch/at91sam9g45_matrix.h>
14 #include <asm/arch/at91sam9_smc.h>
15 #include <asm/arch/at91_common.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/clk.h>
18 #include <lcd.h>
19 #include <linux/mtd/nand.h>
20 #include <atmel_lcdc.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 /* ------------------------------------------------------------------------- */
25 /*
26  * Miscelaneous platform dependent initialisations
27  */
28 
29 #ifdef CONFIG_CMD_NAND
30 void at91sam9m10g45ek_nand_hw_init(void)
31 {
32 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
33 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
34 	unsigned long csa;
35 
36 	/* Enable CS3 */
37 	csa = readl(&matrix->ebicsa);
38 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
39 	writel(csa, &matrix->ebicsa);
40 
41 	/* Configure SMC CS3 for NAND/SmartMedia */
42 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
43 	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
44 	       &smc->cs[3].setup);
45 	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
46 	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
47 	       &smc->cs[3].pulse);
48 	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
49 	       &smc->cs[3].cycle);
50 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
51 	       AT91_SMC_MODE_EXNW_DISABLE |
52 #ifdef CONFIG_SYS_NAND_DBW_16
53 	       AT91_SMC_MODE_DBW_16 |
54 #else /* CONFIG_SYS_NAND_DBW_8 */
55 	       AT91_SMC_MODE_DBW_8 |
56 #endif
57 	       AT91_SMC_MODE_TDF_CYCLE(3),
58 	       &smc->cs[3].mode);
59 
60 	at91_periph_clk_enable(ATMEL_ID_PIOC);
61 
62 	/* Configure RDY/BSY */
63 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
64 
65 	/* Enable NandFlash */
66 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
67 }
68 #endif
69 
70 #if defined(CONFIG_SPL_BUILD)
71 #include <spl.h>
72 #include <nand.h>
73 
74 void at91_spl_board_init(void)
75 {
76 	/*
77 	 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
78 	 * test mode, so it needs do some action to exit test mode.
79 	 */
80 	at91_periph_clk_enable(ATMEL_ID_PIODE);
81 	at91_set_gpio_output(AT91_PIN_PD7, 0);
82 	at91_set_gpio_output(AT91_PIN_PD8, 0);
83 	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
84 	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
85 
86 #ifdef CONFIG_SYS_USE_MMC
87 	at91_mci_hw_init();
88 #elif CONFIG_SYS_USE_NANDFLASH
89 	at91sam9m10g45ek_nand_hw_init();
90 #endif
91 }
92 
93 #include <asm/arch/atmel_mpddrc.h>
94 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
95 {
96 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
97 
98 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
99 		    ATMEL_MPDDRC_CR_NR_ROW_14 |
100 		    ATMEL_MPDDRC_CR_DQMS_SHARED |
101 		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
102 
103 	ddr2->rtr = 0x24b;
104 
105 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
106 		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
107 		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
108 		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
109 		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
110 		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
111 		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
112 		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
113 
114 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
115 		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
116 		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
117 		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
118 
119 	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
120 		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
121 		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
122 		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
123 }
124 
125 void mem_init(void)
126 {
127 	struct atmel_mpddrc_config ddr2;
128 
129 	ddr2_conf(&ddr2);
130 
131 	at91_system_clk_enable(AT91_PMC_DDR);
132 
133 	/* DDRAM2 Controller initialize */
134 	ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
135 }
136 #endif
137 
138 #ifdef CONFIG_CMD_USB
139 static void at91sam9m10g45ek_usb_hw_init(void)
140 {
141 	at91_periph_clk_enable(ATMEL_ID_PIODE);
142 
143 	at91_set_gpio_output(AT91_PIN_PD1, 0);
144 	at91_set_gpio_output(AT91_PIN_PD3, 0);
145 }
146 #endif
147 
148 #ifdef CONFIG_LCD
149 
150 vidinfo_t panel_info = {
151 	.vl_col =		480,
152 	.vl_row =		272,
153 	.vl_clk =		9000000,
154 	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
155 				ATMEL_LCDC_INVFRAME_NORMAL,
156 	.vl_bpix =		3,
157 	.vl_tft =		1,
158 	.vl_hsync_len =		45,
159 	.vl_left_margin =	1,
160 	.vl_right_margin =	1,
161 	.vl_vsync_len =		1,
162 	.vl_upper_margin =	40,
163 	.vl_lower_margin =	1,
164 	.mmio =			ATMEL_BASE_LCDC,
165 };
166 
167 
168 void lcd_enable(void)
169 {
170 	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
171 }
172 
173 void lcd_disable(void)
174 {
175 	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
176 }
177 
178 static void at91sam9m10g45ek_lcd_hw_init(void)
179 {
180 	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
181 	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
182 	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
183 	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
184 	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
185 
186 	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
187 	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
188 	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
189 	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
190 	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
191 	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
192 	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
193 	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
194 	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
195 	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
196 	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
197 	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
198 	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
199 	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
200 	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
201 	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
202 	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
203 	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
204 	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
205 	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
206 	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
207 	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
208 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
209 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
210 
211 	at91_periph_clk_enable(ATMEL_ID_LCDC);
212 
213 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
214 }
215 
216 #ifdef CONFIG_LCD_INFO
217 #include <nand.h>
218 #include <version.h>
219 
220 void lcd_show_board_info(void)
221 {
222 	ulong dram_size, nand_size;
223 	int i;
224 	char temp[32];
225 
226 	lcd_printf ("%s\n", U_BOOT_VERSION);
227 	lcd_printf ("(C) 2008 ATMEL Corp\n");
228 	lcd_printf ("at91support@atmel.com\n");
229 	lcd_printf ("%s CPU at %s MHz\n",
230 		ATMEL_CPU_NAME,
231 		strmhz(temp, get_cpu_clk_rate()));
232 
233 	dram_size = 0;
234 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
235 		dram_size += gd->bd->bi_dram[i].size;
236 	nand_size = 0;
237 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
238 		nand_size += nand_info[i]->size;
239 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
240 		dram_size >> 20,
241 		nand_size >> 20 );
242 }
243 #endif /* CONFIG_LCD_INFO */
244 #endif
245 
246 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
247 void board_debug_uart_init(void)
248 {
249 	at91_seriald_hw_init();
250 }
251 #endif
252 
253 #ifdef CONFIG_BOARD_EARLY_INIT_F
254 int board_early_init_f(void)
255 {
256 #ifdef CONFIG_DEBUG_UART
257 	debug_uart_init();
258 #endif
259 	return 0;
260 }
261 #endif
262 
263 int board_init(void)
264 {
265 	/* arch number of AT91SAM9M10G45EK-Board */
266 #ifdef CONFIG_AT91SAM9M10G45EK
267 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
268 #elif defined CONFIG_AT91SAM9G45EKES
269 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
270 #endif
271 
272 	/* adress of boot parameters */
273 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
274 
275 #ifdef CONFIG_CMD_NAND
276 	at91sam9m10g45ek_nand_hw_init();
277 #endif
278 #ifdef CONFIG_CMD_USB
279 	at91sam9m10g45ek_usb_hw_init();
280 #endif
281 #ifdef CONFIG_LCD
282 	at91sam9m10g45ek_lcd_hw_init();
283 #endif
284 	return 0;
285 }
286 
287 int dram_init(void)
288 {
289 	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
290 				    CONFIG_SYS_SDRAM_SIZE);
291 	return 0;
292 }
293 
294 #ifdef CONFIG_RESET_PHY_R
295 void reset_phy(void)
296 {
297 }
298 #endif
299