1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/at91sam9g45_matrix.h> 12 #include <asm/arch/at91sam9_smc.h> 13 #include <asm/arch/at91_common.h> 14 #include <asm/arch/at91_pmc.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/clk.h> 17 #include <lcd.h> 18 #include <atmel_lcdc.h> 19 #include <atmel_mci.h> 20 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 21 #include <net.h> 22 #endif 23 #include <netdev.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 /* ------------------------------------------------------------------------- */ 28 /* 29 * Miscelaneous platform dependent initialisations 30 */ 31 32 #ifdef CONFIG_CMD_NAND 33 void at91sam9m10g45ek_nand_hw_init(void) 34 { 35 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 36 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 37 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 38 unsigned long csa; 39 40 /* Enable CS3 */ 41 csa = readl(&matrix->ebicsa); 42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; 43 writel(csa, &matrix->ebicsa); 44 45 /* Configure SMC CS3 for NAND/SmartMedia */ 46 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 48 &smc->cs[3].setup); 49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | 50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), 51 &smc->cs[3].pulse); 52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), 53 &smc->cs[3].cycle); 54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 55 AT91_SMC_MODE_EXNW_DISABLE | 56 #ifdef CONFIG_SYS_NAND_DBW_16 57 AT91_SMC_MODE_DBW_16 | 58 #else /* CONFIG_SYS_NAND_DBW_8 */ 59 AT91_SMC_MODE_DBW_8 | 60 #endif 61 AT91_SMC_MODE_TDF_CYCLE(3), 62 &smc->cs[3].mode); 63 64 writel(1 << ATMEL_ID_PIOC, &pmc->pcer); 65 66 /* Configure RDY/BSY */ 67 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 68 69 /* Enable NandFlash */ 70 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 71 } 72 #endif 73 74 #ifdef CONFIG_CMD_USB 75 static void at91sam9m10g45ek_usb_hw_init(void) 76 { 77 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 78 79 writel(1 << ATMEL_ID_PIODE, &pmc->pcer); 80 81 at91_set_gpio_output(AT91_PIN_PD1, 0); 82 at91_set_gpio_output(AT91_PIN_PD3, 0); 83 } 84 #endif 85 86 #ifdef CONFIG_MACB 87 static void at91sam9m10g45ek_macb_hw_init(void) 88 { 89 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 90 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; 91 92 /* Enable clock */ 93 writel(1 << ATMEL_ID_EMAC, &pmc->pcer); 94 95 /* 96 * Disable pull-up on: 97 * RXDV (PA15) => PHY normal mode (not Test mode) 98 * ERX0 (PA12) => PHY ADDR0 99 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 100 * 101 * PHY has internal pull-down 102 */ 103 writel(pin_to_mask(AT91_PIN_PA15) | 104 pin_to_mask(AT91_PIN_PA12) | 105 pin_to_mask(AT91_PIN_PA13), 106 &pioa->pudr); 107 108 at91_phy_reset(); 109 110 /* Re-enable pull-up */ 111 writel(pin_to_mask(AT91_PIN_PA15) | 112 pin_to_mask(AT91_PIN_PA12) | 113 pin_to_mask(AT91_PIN_PA13), 114 &pioa->puer); 115 116 /* And the pins. */ 117 at91_macb_hw_init(); 118 } 119 #endif 120 121 #ifdef CONFIG_LCD 122 123 vidinfo_t panel_info = { 124 .vl_col = 480, 125 .vl_row = 272, 126 .vl_clk = 9000000, 127 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | 128 ATMEL_LCDC_INVFRAME_NORMAL, 129 .vl_bpix = 3, 130 .vl_tft = 1, 131 .vl_hsync_len = 45, 132 .vl_left_margin = 1, 133 .vl_right_margin = 1, 134 .vl_vsync_len = 1, 135 .vl_upper_margin = 40, 136 .vl_lower_margin = 1, 137 .mmio = ATMEL_BASE_LCDC, 138 }; 139 140 141 void lcd_enable(void) 142 { 143 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ 144 } 145 146 void lcd_disable(void) 147 { 148 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ 149 } 150 151 static void at91sam9m10g45ek_lcd_hw_init(void) 152 { 153 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; 154 155 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ 156 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ 157 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ 158 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ 159 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ 160 161 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ 162 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ 163 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ 164 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ 165 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ 166 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ 167 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ 168 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ 169 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ 170 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ 171 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ 172 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ 173 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ 174 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ 175 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ 176 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ 177 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ 178 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ 179 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ 180 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ 181 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ 182 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ 183 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ 184 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ 185 186 writel(1 << ATMEL_ID_LCDC, &pmc->pcer); 187 188 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; 189 } 190 191 #ifdef CONFIG_LCD_INFO 192 #include <nand.h> 193 #include <version.h> 194 195 void lcd_show_board_info(void) 196 { 197 ulong dram_size, nand_size; 198 int i; 199 char temp[32]; 200 201 lcd_printf ("%s\n", U_BOOT_VERSION); 202 lcd_printf ("(C) 2008 ATMEL Corp\n"); 203 lcd_printf ("at91support@atmel.com\n"); 204 lcd_printf ("%s CPU at %s MHz\n", 205 ATMEL_CPU_NAME, 206 strmhz(temp, get_cpu_clk_rate())); 207 208 dram_size = 0; 209 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 210 dram_size += gd->bd->bi_dram[i].size; 211 nand_size = 0; 212 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 213 nand_size += nand_info[i].size; 214 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 215 dram_size >> 20, 216 nand_size >> 20 ); 217 } 218 #endif /* CONFIG_LCD_INFO */ 219 #endif 220 221 #ifdef CONFIG_GENERIC_ATMEL_MCI 222 int board_mmc_init(bd_t *bis) 223 { 224 at91_mci_hw_init(); 225 226 return atmel_mci_init((void *)ATMEL_BASE_MCI0); 227 } 228 #endif 229 230 int board_early_init_f(void) 231 { 232 at91_seriald_hw_init(); 233 return 0; 234 } 235 236 int board_init(void) 237 { 238 /* arch number of AT91SAM9M10G45EK-Board */ 239 #ifdef CONFIG_AT91SAM9M10G45EK 240 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK; 241 #elif defined CONFIG_AT91SAM9G45EKES 242 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; 243 #endif 244 245 /* adress of boot parameters */ 246 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 247 248 #ifdef CONFIG_CMD_NAND 249 at91sam9m10g45ek_nand_hw_init(); 250 #endif 251 #ifdef CONFIG_CMD_USB 252 at91sam9m10g45ek_usb_hw_init(); 253 #endif 254 #ifdef CONFIG_HAS_DATAFLASH 255 at91_spi0_hw_init(1 << 0); 256 #endif 257 #ifdef CONFIG_ATMEL_SPI 258 at91_spi0_hw_init(1 << 4); 259 #endif 260 #ifdef CONFIG_MACB 261 at91sam9m10g45ek_macb_hw_init(); 262 #endif 263 #ifdef CONFIG_LCD 264 at91sam9m10g45ek_lcd_hw_init(); 265 #endif 266 return 0; 267 } 268 269 int dram_init(void) 270 { 271 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, 272 CONFIG_SYS_SDRAM_SIZE); 273 return 0; 274 } 275 276 #ifdef CONFIG_RESET_PHY_R 277 void reset_phy(void) 278 { 279 } 280 #endif 281 282 int board_eth_init(bd_t *bis) 283 { 284 int rc = 0; 285 #ifdef CONFIG_MACB 286 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); 287 #endif 288 return rc; 289 } 290 291 /* SPI chip select control */ 292 #ifdef CONFIG_ATMEL_SPI 293 #include <spi.h> 294 295 int spi_cs_is_valid(unsigned int bus, unsigned int cs) 296 { 297 return bus == 0 && cs < 2; 298 } 299 300 void spi_cs_activate(struct spi_slave *slave) 301 { 302 switch(slave->cs) { 303 case 1: 304 at91_set_gpio_output(AT91_PIN_PB18, 0); 305 break; 306 case 0: 307 default: 308 at91_set_gpio_output(AT91_PIN_PB3, 0); 309 break; 310 } 311 } 312 313 void spi_cs_deactivate(struct spi_slave *slave) 314 { 315 switch(slave->cs) { 316 case 1: 317 at91_set_gpio_output(AT91_PIN_PB18, 1); 318 break; 319 case 0: 320 default: 321 at91_set_gpio_output(AT91_PIN_PB3, 1); 322 break; 323 } 324 } 325 #endif /* CONFIG_ATMEL_SPI */ 326