1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian.pop@leadtechdesign.com>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24 
25 #include <common.h>
26 #include <asm/sizes.h>
27 #include <asm/arch/at91sam9263.h>
28 #include <asm/arch/at91sam9263_matrix.h>
29 #include <asm/arch/at91sam9_smc.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/io.h>
34 #include <asm/arch/hardware.h>
35 #include <lcd.h>
36 #include <atmel_lcdc.h>
37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
38 #include <net.h>
39 #endif
40 #include <netdev.h>
41 
42 DECLARE_GLOBAL_DATA_PTR;
43 
44 /* ------------------------------------------------------------------------- */
45 /*
46  * Miscelaneous platform dependent initialisations
47  */
48 
49 static void at91sam9263ek_serial_hw_init(void)
50 {
51 #ifdef CONFIG_USART0
52 	at91_set_A_periph(AT91_PIN_PA26, 1);		/* TXD0 */
53 	at91_set_A_periph(AT91_PIN_PA27, 0);		/* RXD0 */
54 	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
55 #endif
56 
57 #ifdef CONFIG_USART1
58 	at91_set_A_periph(AT91_PIN_PD0, 1);		/* TXD1 */
59 	at91_set_A_periph(AT91_PIN_PD1, 0);		/* RXD1 */
60 	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
61 #endif
62 
63 #ifdef CONFIG_USART2
64 	at91_set_A_periph(AT91_PIN_PD2, 1);		/* TXD2 */
65 	at91_set_A_periph(AT91_PIN_PD3, 0);		/* RXD2 */
66 	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
67 #endif
68 
69 #ifdef CONFIG_USART3	/* DBGU */
70 	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
71 	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
72 	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
73 #endif
74 }
75 
76 #ifdef CONFIG_CMD_NAND
77 static void at91sam9263ek_nand_hw_init(void)
78 {
79 	unsigned long csa;
80 
81 	/* Enable CS3 */
82 	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
83 	at91_sys_write(AT91_MATRIX_EBI0CSA,
84 		       csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
85 
86 	/* Configure SMC CS3 for NAND/SmartMedia */
87 	at91_sys_write(AT91_SMC_SETUP(3),
88 		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
89 		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
90 	at91_sys_write(AT91_SMC_PULSE(3),
91 		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
92 		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
93 	at91_sys_write(AT91_SMC_CYCLE(3),
94 		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
95 	at91_sys_write(AT91_SMC_MODE(3),
96 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
97 		       AT91_SMC_EXNWMODE_DISABLE |
98 #ifdef CFG_NAND_DBW_16
99 		       AT91_SMC_DBW_16 |
100 #else /* CFG_NAND_DBW_8 */
101 		       AT91_SMC_DBW_8 |
102 #endif
103 		       AT91_SMC_TDF_(2));
104 
105 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
106 				      1 << AT91SAM9263_ID_PIOCDE);
107 
108 	/* Configure RDY/BSY */
109 	at91_set_gpio_input(AT91_PIN_PA22, 1);
110 
111 	/* Enable NandFlash */
112 	at91_set_gpio_output(AT91_PIN_PD15, 1);
113 }
114 #endif
115 
116 #ifdef CONFIG_HAS_DATAFLASH
117 static void at91sam9263ek_spi_hw_init(void)
118 {
119 	at91_set_B_periph(AT91_PIN_PA5, 0);	/* SPI0_NPCS0 */
120 
121 	at91_set_B_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
122 	at91_set_B_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
123 	at91_set_B_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
124 
125 	/* Enable clock */
126 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
127 }
128 #endif
129 
130 #ifdef CONFIG_MACB
131 static void at91sam9263ek_macb_hw_init(void)
132 {
133 	/* Enable clock */
134 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
135 
136 	/*
137 	 * Disable pull-up on:
138 	 *	RXDV (PC25) => PHY normal mode (not Test mode)
139 	 * 	ERX0 (PE25) => PHY ADDR0
140 	 *	ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
141 	 *
142 	 * PHY has internal pull-down
143 	 */
144 	writel(pin_to_mask(AT91_PIN_PC25),
145 	       pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
146 	writel(pin_to_mask(AT91_PIN_PE25) |
147 	       pin_to_mask(AT91_PIN_PE26),
148 	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
149 
150 	/* Need to reset PHY -> 500ms reset */
151 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
152 				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
153 				     AT91_RSTC_URSTEN);
154 
155 	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
156 
157 	/* Wait for end hardware reset */
158 	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
159 
160 	/* Restore NRST value */
161 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
162 				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
163 				     AT91_RSTC_URSTEN);
164 
165 	/* Re-enable pull-up */
166 	writel(pin_to_mask(AT91_PIN_PC25),
167 	       pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
168 	writel(pin_to_mask(AT91_PIN_PE25) |
169 	       pin_to_mask(AT91_PIN_PE26),
170 	       pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
171 
172 	at91_set_A_periph(AT91_PIN_PE21, 0);	/* ETXCK_EREFCK */
173 	at91_set_B_periph(AT91_PIN_PC25, 0);	/* ERXDV */
174 	at91_set_A_periph(AT91_PIN_PE25, 0);	/* ERX0 */
175 	at91_set_A_periph(AT91_PIN_PE26, 0);	/* ERX1 */
176 	at91_set_A_periph(AT91_PIN_PE27, 0);	/* ERXER */
177 	at91_set_A_periph(AT91_PIN_PE28, 0);	/* ETXEN */
178 	at91_set_A_periph(AT91_PIN_PE23, 0);	/* ETX0 */
179 	at91_set_A_periph(AT91_PIN_PE24, 0);	/* ETX1 */
180 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* EMDIO */
181 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* EMDC */
182 
183 #ifndef CONFIG_RMII
184 	at91_set_A_periph(AT91_PIN_PE22, 0);	/* ECRS */
185 	at91_set_B_periph(AT91_PIN_PC26, 0);	/* ECOL */
186 	at91_set_B_periph(AT91_PIN_PC22, 0);	/* ERX2 */
187 	at91_set_B_periph(AT91_PIN_PC23, 0);	/* ERX3 */
188 	at91_set_B_periph(AT91_PIN_PC27, 0);	/* ERXCK */
189 	at91_set_B_periph(AT91_PIN_PC20, 0);	/* ETX2 */
190 	at91_set_B_periph(AT91_PIN_PC21, 0);	/* ETX3 */
191 	at91_set_B_periph(AT91_PIN_PC24, 0);	/* ETXER */
192 #endif
193 
194 }
195 #endif
196 
197 #ifdef CONFIG_USB_OHCI_NEW
198 static void at91sam9263ek_uhp_hw_init(void)
199 {
200 	/* Enable VBus on UHP ports */
201 	at91_set_gpio_output(AT91_PIN_PA21, 0);
202 	at91_set_gpio_output(AT91_PIN_PA24, 0);
203 }
204 #endif
205 
206 #ifdef CONFIG_LCD
207 vidinfo_t panel_info = {
208 	vl_col:		240,
209 	vl_row:		320,
210 	vl_clk:		4965000,
211 	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
212 			ATMEL_LCDC_INVFRAME_INVERTED,
213 	vl_bpix:	3,
214 	vl_tft:		1,
215 	vl_hsync_len:	5,
216 	vl_left_margin:	1,
217 	vl_right_margin:33,
218 	vl_vsync_len:	1,
219 	vl_upper_margin:1,
220 	vl_lower_margin:0,
221 	mmio:		AT91SAM9263_LCDC_BASE,
222 };
223 
224 void lcd_enable(void)
225 {
226 	at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
227 }
228 
229 void lcd_disable(void)
230 {
231 	at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
232 }
233 
234 static void at91sam9263ek_lcd_hw_init(void)
235 {
236 	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
237 	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
238 	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
239 	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
240 	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
241 	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
242 	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
243 	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
244 	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
245 	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
246 	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
247 	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
248 	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
249 	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
250 	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
251 	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
252 	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
253 	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
254 	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
255 	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
256 	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
257 	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
258 
259 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
260 
261 	gd->fb_base = AT91SAM9263_SRAM0_BASE;
262 }
263 #endif
264 
265 int board_init(void)
266 {
267 	/* Enable Ctrlc */
268 	console_init_f();
269 
270 	/* arch number of AT91SAM9263EK-Board */
271 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
272 	/* adress of boot parameters */
273 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
274 
275 	at91sam9263ek_serial_hw_init();
276 #ifdef CONFIG_CMD_NAND
277 	at91sam9263ek_nand_hw_init();
278 #endif
279 #ifdef CONFIG_HAS_DATAFLASH
280 	at91sam9263ek_spi_hw_init();
281 #endif
282 #ifdef CONFIG_MACB
283 	at91sam9263ek_macb_hw_init();
284 #endif
285 #ifdef CONFIG_USB_OHCI_NEW
286 	at91sam9263ek_uhp_hw_init();
287 #endif
288 #ifdef CONFIG_LCD
289 	at91sam9263ek_lcd_hw_init();
290 #endif
291 	return 0;
292 }
293 
294 int dram_init(void)
295 {
296 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
297 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
298 	return 0;
299 }
300 
301 #ifdef CONFIG_RESET_PHY_R
302 void reset_phy(void)
303 {
304 #ifdef CONFIG_MACB
305 	/*
306 	 * Initialize ethernet HW addr prior to starting Linux,
307 	 * needed for nfsroot
308 	 */
309 	eth_init(gd->bd);
310 #endif
311 }
312 #endif
313 
314 int board_eth_init(bd_t *bis)
315 {
316 	int rc = 0;
317 #ifdef CONFIG_MACB
318 	rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x00);
319 #endif
320 	return rc;
321 }
322