1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2007-2008 4 * Stelian Pop <stelian@popies.net> 5 * Lead Tech Design <www.leadtechdesign.com> 6 */ 7 8 #include <common.h> 9 #include <debug_uart.h> 10 #include <linux/sizes.h> 11 #include <asm/arch/at91sam9263.h> 12 #include <asm/arch/at91sam9_smc.h> 13 #include <asm/arch/at91_common.h> 14 #include <asm/arch/at91_matrix.h> 15 #include <asm/arch/at91_pio.h> 16 #include <asm/arch/clk.h> 17 #include <asm/io.h> 18 #include <asm/arch/gpio.h> 19 #include <asm/arch/hardware.h> 20 #include <lcd.h> 21 #include <atmel_lcdc.h> 22 #include <asm/mach-types.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 /* ------------------------------------------------------------------------- */ 27 /* 28 * Miscelaneous platform dependent initialisations 29 */ 30 31 #ifdef CONFIG_CMD_NAND 32 static void at91sam9263ek_nand_hw_init(void) 33 { 34 unsigned long csa; 35 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; 36 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; 37 38 /* Enable CS3 */ 39 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; 40 writel(csa, &matrix->csa[0]); 41 42 /* Enable CS3 */ 43 44 /* Configure SMC CS3 for NAND/SmartMedia */ 45 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 46 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 47 &smc->cs[3].setup); 48 49 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 51 &smc->cs[3].pulse); 52 53 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 54 &smc->cs[3].cycle); 55 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 56 AT91_SMC_MODE_EXNW_DISABLE | 57 #ifdef CONFIG_SYS_NAND_DBW_16 58 AT91_SMC_MODE_DBW_16 | 59 #else /* CONFIG_SYS_NAND_DBW_8 */ 60 AT91_SMC_MODE_DBW_8 | 61 #endif 62 AT91_SMC_MODE_TDF_CYCLE(2), 63 &smc->cs[3].mode); 64 65 at91_periph_clk_enable(ATMEL_ID_PIOA); 66 at91_periph_clk_enable(ATMEL_ID_PIOCDE); 67 68 /* Configure RDY/BSY */ 69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 70 71 /* Enable NandFlash */ 72 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 73 } 74 #endif 75 76 #ifdef CONFIG_LCD 77 vidinfo_t panel_info = { 78 .vl_col = 240, 79 .vl_row = 320, 80 .vl_clk = 4965000, 81 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | 82 ATMEL_LCDC_INVFRAME_INVERTED, 83 .vl_bpix = 3, 84 .vl_tft = 1, 85 .vl_hsync_len = 5, 86 .vl_left_margin = 1, 87 .vl_right_margin = 33, 88 .vl_vsync_len = 1, 89 .vl_upper_margin = 1, 90 .vl_lower_margin = 0, 91 .mmio = ATMEL_BASE_LCDC, 92 }; 93 94 void lcd_enable(void) 95 { 96 at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */ 97 } 98 99 void lcd_disable(void) 100 { 101 at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */ 102 } 103 104 static void at91sam9263ek_lcd_hw_init(void) 105 { 106 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ 107 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ 108 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ 109 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ 110 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ 111 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ 112 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ 113 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ 114 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ 115 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ 116 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ 117 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ 118 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ 119 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ 120 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ 121 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ 122 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ 123 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ 124 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ 125 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ 126 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ 127 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ 128 129 at91_periph_clk_enable(ATMEL_ID_LCDC); 130 gd->fb_base = ATMEL_BASE_SRAM0; 131 } 132 133 #ifdef CONFIG_LCD_INFO 134 #include <nand.h> 135 #include <version.h> 136 137 #ifdef CONFIG_MTD_NOR_FLASH 138 extern flash_info_t flash_info[]; 139 #endif 140 141 void lcd_show_board_info(void) 142 { 143 ulong dram_size, nand_size; 144 #ifdef CONFIG_MTD_NOR_FLASH 145 ulong flash_size; 146 #endif 147 int i; 148 char temp[32]; 149 150 lcd_printf ("%s\n", U_BOOT_VERSION); 151 lcd_printf ("(C) 2008 ATMEL Corp\n"); 152 lcd_printf ("at91support@atmel.com\n"); 153 lcd_printf ("%s CPU at %s MHz\n", 154 ATMEL_CPU_NAME, 155 strmhz(temp, get_cpu_clk_rate())); 156 157 dram_size = 0; 158 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 159 dram_size += gd->bd->bi_dram[i].size; 160 nand_size = 0; 161 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 162 nand_size += get_nand_dev_by_index(i)->size; 163 #ifdef CONFIG_MTD_NOR_FLASH 164 flash_size = 0; 165 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) 166 flash_size += flash_info[i].size; 167 #endif 168 lcd_printf (" %ld MB SDRAM, %ld MB NAND", 169 dram_size >> 20, 170 nand_size >> 20 ); 171 #ifdef CONFIG_MTD_NOR_FLASH 172 lcd_printf (",\n %ld MB NOR", 173 flash_size >> 20); 174 #endif 175 lcd_puts ("\n"); 176 } 177 #endif /* CONFIG_LCD_INFO */ 178 #endif 179 180 #ifdef CONFIG_DEBUG_UART_BOARD_INIT 181 void board_debug_uart_init(void) 182 { 183 at91_seriald_hw_init(); 184 } 185 #endif 186 187 #ifdef CONFIG_BOARD_EARLY_INIT_F 188 int board_early_init_f(void) 189 { 190 #ifdef CONFIG_DEBUG_UART 191 debug_uart_init(); 192 #endif 193 return 0; 194 } 195 #endif 196 197 int board_init(void) 198 { 199 /* arch number of AT91SAM9263EK-Board */ 200 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; 201 /* adress of boot parameters */ 202 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 203 204 #ifdef CONFIG_CMD_NAND 205 at91sam9263ek_nand_hw_init(); 206 #endif 207 #ifdef CONFIG_USB_OHCI_NEW 208 at91_uhp_hw_init(); 209 #endif 210 #ifdef CONFIG_LCD 211 at91sam9263ek_lcd_hw_init(); 212 #endif 213 return 0; 214 } 215 216 int dram_init(void) 217 { 218 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 219 CONFIG_SYS_SDRAM_SIZE); 220 221 return 0; 222 } 223 224 #ifdef CONFIG_RESET_PHY_R 225 void reset_phy(void) 226 { 227 } 228 #endif 229