1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <debug_uart.h>
11 #include <linux/sizes.h>
12 #include <asm/arch/at91sam9263.h>
13 #include <asm/arch/at91sam9_smc.h>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91_matrix.h>
16 #include <asm/arch/at91_pio.h>
17 #include <asm/arch/clk.h>
18 #include <asm/io.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/hardware.h>
21 #include <lcd.h>
22 #include <atmel_lcdc.h>
23 #include <asm/mach-types.h>
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 /* ------------------------------------------------------------------------- */
28 /*
29  * Miscelaneous platform dependent initialisations
30  */
31 
32 #ifdef CONFIG_CMD_NAND
33 static void at91sam9263ek_nand_hw_init(void)
34 {
35 	unsigned long csa;
36 	at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
37 	at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
38 
39 	/* Enable CS3 */
40 	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
41 	writel(csa, &matrix->csa[0]);
42 
43 	/* Enable CS3 */
44 
45 	/* Configure SMC CS3 for NAND/SmartMedia */
46 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
47 		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
48 		&smc->cs[3].setup);
49 
50 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
51 		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
52 		&smc->cs[3].pulse);
53 
54 	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
55 		&smc->cs[3].cycle);
56 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
57 		AT91_SMC_MODE_EXNW_DISABLE |
58 #ifdef CONFIG_SYS_NAND_DBW_16
59 		       AT91_SMC_MODE_DBW_16 |
60 #else /* CONFIG_SYS_NAND_DBW_8 */
61 		       AT91_SMC_MODE_DBW_8 |
62 #endif
63 		       AT91_SMC_MODE_TDF_CYCLE(2),
64 		&smc->cs[3].mode);
65 
66 	at91_periph_clk_enable(ATMEL_ID_PIOA);
67 	at91_periph_clk_enable(ATMEL_ID_PIOCDE);
68 
69 	/* Configure RDY/BSY */
70 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
71 
72 	/* Enable NandFlash */
73 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
74 }
75 #endif
76 
77 #ifdef CONFIG_LCD
78 vidinfo_t panel_info = {
79 	.vl_col =		240,
80 	.vl_row =		320,
81 	.vl_clk =		4965000,
82 	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
83 				ATMEL_LCDC_INVFRAME_INVERTED,
84 	.vl_bpix =		3,
85 	.vl_tft =		1,
86 	.vl_hsync_len =		5,
87 	.vl_left_margin =	1,
88 	.vl_right_margin =	33,
89 	.vl_vsync_len =		1,
90 	.vl_upper_margin =	1,
91 	.vl_lower_margin =	0,
92 	.mmio =			ATMEL_BASE_LCDC,
93 };
94 
95 void lcd_enable(void)
96 {
97 	at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
98 }
99 
100 void lcd_disable(void)
101 {
102 	at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
103 }
104 
105 static void at91sam9263ek_lcd_hw_init(void)
106 {
107 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
108 	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
109 	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
110 	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
111 	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
112 	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
113 	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
114 	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
115 	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
116 	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
117 	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
118 	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
119 	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
120 	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
121 	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
122 	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
123 	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
124 	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
125 	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
126 	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
127 	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
128 	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
129 
130 	at91_periph_clk_enable(ATMEL_ID_LCDC);
131 	gd->fb_base = ATMEL_BASE_SRAM0;
132 }
133 
134 #ifdef CONFIG_LCD_INFO
135 #include <nand.h>
136 #include <version.h>
137 
138 #ifdef CONFIG_MTD_NOR_FLASH
139 extern flash_info_t flash_info[];
140 #endif
141 
142 void lcd_show_board_info(void)
143 {
144 	ulong dram_size, nand_size;
145 #ifdef CONFIG_MTD_NOR_FLASH
146 	ulong flash_size;
147 #endif
148 	int i;
149 	char temp[32];
150 
151 	lcd_printf ("%s\n", U_BOOT_VERSION);
152 	lcd_printf ("(C) 2008 ATMEL Corp\n");
153 	lcd_printf ("at91support@atmel.com\n");
154 	lcd_printf ("%s CPU at %s MHz\n",
155 		ATMEL_CPU_NAME,
156 		strmhz(temp, get_cpu_clk_rate()));
157 
158 	dram_size = 0;
159 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
160 		dram_size += gd->bd->bi_dram[i].size;
161 	nand_size = 0;
162 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
163 		nand_size += get_nand_dev_by_index(i)->size;
164 #ifdef CONFIG_MTD_NOR_FLASH
165 	flash_size = 0;
166 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
167 		flash_size += flash_info[i].size;
168 #endif
169 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
170 		dram_size >> 20,
171 		nand_size >> 20 );
172 #ifdef CONFIG_MTD_NOR_FLASH
173 	lcd_printf (",\n  %ld MB NOR",
174 		flash_size >> 20);
175 #endif
176 	lcd_puts ("\n");
177 }
178 #endif /* CONFIG_LCD_INFO */
179 #endif
180 
181 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
182 void board_debug_uart_init(void)
183 {
184 	at91_seriald_hw_init();
185 }
186 #endif
187 
188 #ifdef CONFIG_BOARD_EARLY_INIT_F
189 int board_early_init_f(void)
190 {
191 #ifdef CONFIG_DEBUG_UART
192 	debug_uart_init();
193 #endif
194 	return 0;
195 }
196 #endif
197 
198 int board_init(void)
199 {
200 	/* arch number of AT91SAM9263EK-Board */
201 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
202 	/* adress of boot parameters */
203 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
204 
205 #ifdef CONFIG_CMD_NAND
206 	at91sam9263ek_nand_hw_init();
207 #endif
208 #ifdef CONFIG_USB_OHCI_NEW
209 	at91_uhp_hw_init();
210 #endif
211 #ifdef CONFIG_LCD
212 	at91sam9263ek_lcd_hw_init();
213 #endif
214 	return 0;
215 }
216 
217 int dram_init(void)
218 {
219 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
220 		CONFIG_SYS_SDRAM_SIZE);
221 
222 	return 0;
223 }
224 
225 #ifdef CONFIG_RESET_PHY_R
226 void reset_phy(void)
227 {
228 }
229 #endif
230