1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9261.h> 27 #include <asm/arch/at91sam9261_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_common.h> 30 #include <asm/arch/at91_pmc.h> 31 #include <asm/arch/at91_rstc.h> 32 #include <asm/arch/clk.h> 33 #include <asm/arch/gpio.h> 34 #include <asm/arch/io.h> 35 #include <lcd.h> 36 #include <atmel_lcdc.h> 37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) 38 #include <net.h> 39 #include <netdev.h> 40 #endif 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* ------------------------------------------------------------------------- */ 45 /* 46 * Miscelaneous platform dependent initialisations 47 */ 48 49 #ifdef CONFIG_CMD_NAND 50 static void at91sam9261ek_nand_hw_init(void) 51 { 52 unsigned long csa; 53 54 /* Enable CS3 */ 55 csa = at91_sys_read(AT91_MATRIX_EBICSA); 56 at91_sys_write(AT91_MATRIX_EBICSA, 57 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 58 59 /* Configure SMC CS3 for NAND/SmartMedia */ 60 #ifdef CONFIG_AT91SAM9G10EK 61 at91_sys_write(AT91_SMC_SETUP(3), 62 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | 63 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); 64 at91_sys_write(AT91_SMC_PULSE(3), 65 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(7) | 66 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(7)); 67 at91_sys_write(AT91_SMC_CYCLE(3), 68 AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); 69 #else 70 at91_sys_write(AT91_SMC_SETUP(3), 71 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 72 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 73 at91_sys_write(AT91_SMC_PULSE(3), 74 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 75 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 76 at91_sys_write(AT91_SMC_CYCLE(3), 77 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 78 #endif 79 at91_sys_write(AT91_SMC_MODE(3), 80 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 81 AT91_SMC_EXNWMODE_DISABLE | 82 #ifdef CONFIG_SYS_NAND_DBW_16 83 AT91_SMC_DBW_16 | 84 #else /* CONFIG_SYS_NAND_DBW_8 */ 85 AT91_SMC_DBW_8 | 86 #endif 87 AT91_SMC_TDF_(2)); 88 89 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); 90 91 /* Configure RDY/BSY */ 92 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 93 94 /* Enable NandFlash */ 95 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 96 97 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ 98 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ 99 } 100 #endif 101 102 #ifdef CONFIG_DRIVER_DM9000 103 static void at91sam9261ek_dm9000_hw_init(void) 104 { 105 /* Configure SMC CS2 for DM9000 */ 106 #ifdef CONFIG_AT91SAM9G10EK 107 at91_sys_write(AT91_SMC_SETUP(2), 108 AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(0) | 109 AT91_SMC_NRDSETUP_(3) | AT91_SMC_NCS_RDSETUP_(0)); 110 at91_sys_write(AT91_SMC_PULSE(2), 111 AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(8) | 112 AT91_SMC_NRDPULSE_(6) | AT91_SMC_NCS_RDPULSE_(8)); 113 at91_sys_write(AT91_SMC_CYCLE(2), 114 AT91_SMC_NWECYCLE_(20) | AT91_SMC_NRDCYCLE_(20)); 115 at91_sys_write(AT91_SMC_MODE(2), 116 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 117 AT91_SMC_EXNWMODE_DISABLE | 118 AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | 119 AT91_SMC_TDF_(1)); 120 #else 121 at91_sys_write(AT91_SMC_SETUP(2), 122 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | 123 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); 124 at91_sys_write(AT91_SMC_PULSE(2), 125 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | 126 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); 127 at91_sys_write(AT91_SMC_CYCLE(2), 128 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); 129 at91_sys_write(AT91_SMC_MODE(2), 130 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 131 AT91_SMC_EXNWMODE_DISABLE | 132 AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | 133 AT91_SMC_TDF_(1)); 134 #endif 135 136 /* Configure Reset signal as output */ 137 at91_set_gpio_output(AT91_PIN_PC10, 0); 138 139 /* Configure Interrupt pin as input, no pull-up */ 140 at91_set_gpio_input(AT91_PIN_PC11, 0); 141 } 142 #endif 143 144 #ifdef CONFIG_LCD 145 vidinfo_t panel_info = { 146 vl_col: 240, 147 vl_row: 320, 148 vl_clk: 4965000, 149 vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 150 ATMEL_LCDC_INVFRAME_INVERTED, 151 vl_bpix: 3, 152 vl_tft: 1, 153 vl_hsync_len: 5, 154 vl_left_margin: 1, 155 vl_right_margin:33, 156 vl_vsync_len: 1, 157 vl_upper_margin:1, 158 vl_lower_margin:0, 159 mmio: AT91SAM9261_LCDC_BASE, 160 }; 161 162 void lcd_enable(void) 163 { 164 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ 165 } 166 167 void lcd_disable(void) 168 { 169 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ 170 } 171 172 static void at91sam9261ek_lcd_hw_init(void) 173 { 174 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ 175 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ 176 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ 177 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ 178 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ 179 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ 180 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ 181 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ 182 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ 183 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ 184 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ 185 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ 186 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ 187 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ 188 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ 189 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ 190 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ 191 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ 192 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ 193 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ 194 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ 195 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ 196 197 at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); 198 199 #ifdef CONFIG_AT91SAM9G10EK 200 gd->fb_base = CONFIG_AT91SAM9G10_LCD_BASE; 201 #else 202 gd->fb_base = AT91SAM9261_SRAM_BASE; 203 #endif 204 } 205 206 #ifdef CONFIG_LCD_INFO 207 #include <nand.h> 208 #include <version.h> 209 210 void lcd_show_board_info(void) 211 { 212 ulong dram_size, nand_size; 213 int i; 214 char temp[32]; 215 216 lcd_printf ("%s\n", U_BOOT_VERSION); 217 lcd_printf ("(C) 2008 ATMEL Corp\n"); 218 lcd_printf ("at91support@atmel.com\n"); 219 lcd_printf ("%s CPU at %s MHz\n", 220 CONFIG_SYS_AT91_CPU_NAME, 221 strmhz(temp, get_cpu_clk_rate())); 222 223 dram_size = 0; 224 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 225 dram_size += gd->bd->bi_dram[i].size; 226 nand_size = 0; 227 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 228 nand_size += nand_info[i].size; 229 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 230 dram_size >> 20, 231 nand_size >> 20 ); 232 } 233 #endif /* CONFIG_LCD_INFO */ 234 #endif 235 236 int board_init(void) 237 { 238 /* Enable Ctrlc */ 239 console_init_f(); 240 241 #ifdef CONFIG_AT91SAM9G10EK 242 /* arch number of AT91SAM9G10EK-Board */ 243 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK; 244 #else 245 /* arch number of AT91SAM9261EK-Board */ 246 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; 247 #endif 248 /* adress of boot parameters */ 249 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 250 251 at91_serial_hw_init(); 252 #ifdef CONFIG_CMD_NAND 253 at91sam9261ek_nand_hw_init(); 254 #endif 255 #ifdef CONFIG_HAS_DATAFLASH 256 at91_spi0_hw_init(1 << 0); 257 #endif 258 #ifdef CONFIG_DRIVER_DM9000 259 at91sam9261ek_dm9000_hw_init(); 260 #endif 261 #ifdef CONFIG_LCD 262 at91sam9261ek_lcd_hw_init(); 263 #endif 264 return 0; 265 } 266 267 #ifdef CONFIG_DRIVER_DM9000 268 int board_eth_init(bd_t *bis) 269 { 270 return dm9000_initialize(bis); 271 } 272 #endif 273 274 int dram_init(void) 275 { 276 gd->bd->bi_dram[0].start = PHYS_SDRAM; 277 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 278 return 0; 279 } 280 281 #ifdef CONFIG_RESET_PHY_R 282 void reset_phy(void) 283 { 284 #ifdef CONFIG_DRIVER_DM9000 285 /* 286 * Initialize ethernet HW addr prior to starting Linux, 287 * needed for nfsroot 288 */ 289 eth_init(gd->bd); 290 #endif 291 } 292 #endif 293