1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9261.h> 27 #include <asm/arch/at91sam9261_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_common.h> 30 #include <asm/arch/at91_pmc.h> 31 #include <asm/arch/at91_rstc.h> 32 #include <asm/arch/clk.h> 33 #include <asm/arch/gpio.h> 34 #include <asm/arch/io.h> 35 #include <lcd.h> 36 #include <atmel_lcdc.h> 37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) 38 #include <net.h> 39 #endif 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 /* ------------------------------------------------------------------------- */ 44 /* 45 * Miscelaneous platform dependent initialisations 46 */ 47 48 #ifdef CONFIG_CMD_NAND 49 static void at91sam9261ek_nand_hw_init(void) 50 { 51 unsigned long csa; 52 53 /* Enable CS3 */ 54 csa = at91_sys_read(AT91_MATRIX_EBICSA); 55 at91_sys_write(AT91_MATRIX_EBICSA, 56 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 57 58 /* Configure SMC CS3 for NAND/SmartMedia */ 59 at91_sys_write(AT91_SMC_SETUP(3), 60 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 61 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 62 at91_sys_write(AT91_SMC_PULSE(3), 63 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 64 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 65 at91_sys_write(AT91_SMC_CYCLE(3), 66 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 67 at91_sys_write(AT91_SMC_MODE(3), 68 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 69 AT91_SMC_EXNWMODE_DISABLE | 70 #ifdef CONFIG_SYS_NAND_DBW_16 71 AT91_SMC_DBW_16 | 72 #else /* CONFIG_SYS_NAND_DBW_8 */ 73 AT91_SMC_DBW_8 | 74 #endif 75 AT91_SMC_TDF_(2)); 76 77 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); 78 79 /* Configure RDY/BSY */ 80 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 81 82 /* Enable NandFlash */ 83 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 84 85 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ 86 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ 87 } 88 #endif 89 90 #ifdef CONFIG_DRIVER_DM9000 91 static void at91sam9261ek_dm9000_hw_init(void) 92 { 93 /* Configure SMC CS2 for DM9000 */ 94 at91_sys_write(AT91_SMC_SETUP(2), 95 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | 96 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); 97 at91_sys_write(AT91_SMC_PULSE(2), 98 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | 99 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); 100 at91_sys_write(AT91_SMC_CYCLE(2), 101 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); 102 at91_sys_write(AT91_SMC_MODE(2), 103 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 104 AT91_SMC_EXNWMODE_DISABLE | 105 AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | 106 AT91_SMC_TDF_(1)); 107 108 /* Configure Reset signal as output */ 109 at91_set_gpio_output(AT91_PIN_PC10, 0); 110 111 /* Configure Interrupt pin as input, no pull-up */ 112 at91_set_gpio_input(AT91_PIN_PC11, 0); 113 } 114 #endif 115 116 #ifdef CONFIG_LCD 117 vidinfo_t panel_info = { 118 vl_col: 240, 119 vl_row: 320, 120 vl_clk: 4965000, 121 vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 122 ATMEL_LCDC_INVFRAME_INVERTED, 123 vl_bpix: 3, 124 vl_tft: 1, 125 vl_hsync_len: 5, 126 vl_left_margin: 1, 127 vl_right_margin:33, 128 vl_vsync_len: 1, 129 vl_upper_margin:1, 130 vl_lower_margin:0, 131 mmio: AT91SAM9261_LCDC_BASE, 132 }; 133 134 void lcd_enable(void) 135 { 136 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ 137 } 138 139 void lcd_disable(void) 140 { 141 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ 142 } 143 144 static void at91sam9261ek_lcd_hw_init(void) 145 { 146 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ 147 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ 148 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ 149 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ 150 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ 151 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ 152 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ 153 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ 154 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ 155 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ 156 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ 157 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ 158 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ 159 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ 160 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ 161 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ 162 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ 163 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ 164 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ 165 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ 166 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ 167 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ 168 169 at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); 170 171 gd->fb_base = AT91SAM9261_SRAM_BASE; 172 } 173 174 #ifdef CONFIG_LCD_INFO 175 #include <nand.h> 176 #include <version.h> 177 178 void lcd_show_board_info(void) 179 { 180 ulong dram_size, nand_size; 181 int i; 182 char temp[32]; 183 184 lcd_printf ("%s\n", U_BOOT_VERSION); 185 lcd_printf ("(C) 2008 ATMEL Corp\n"); 186 lcd_printf ("at91support@atmel.com\n"); 187 lcd_printf ("%s CPU at %s MHz\n", 188 AT91_CPU_NAME, 189 strmhz(temp, get_cpu_clk_rate())); 190 191 dram_size = 0; 192 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 193 dram_size += gd->bd->bi_dram[i].size; 194 nand_size = 0; 195 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 196 nand_size += nand_info[i].size; 197 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 198 dram_size >> 20, 199 nand_size >> 20 ); 200 } 201 #endif /* CONFIG_LCD_INFO */ 202 #endif 203 204 int board_init(void) 205 { 206 /* Enable Ctrlc */ 207 console_init_f(); 208 209 /* arch number of AT91SAM9261EK-Board */ 210 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; 211 /* adress of boot parameters */ 212 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 213 214 at91_serial_hw_init(); 215 #ifdef CONFIG_CMD_NAND 216 at91sam9261ek_nand_hw_init(); 217 #endif 218 #ifdef CONFIG_HAS_DATAFLASH 219 at91_spi0_hw_init(1 << 0); 220 #endif 221 #ifdef CONFIG_DRIVER_DM9000 222 at91sam9261ek_dm9000_hw_init(); 223 #endif 224 #ifdef CONFIG_LCD 225 at91sam9261ek_lcd_hw_init(); 226 #endif 227 return 0; 228 } 229 230 int dram_init(void) 231 { 232 gd->bd->bi_dram[0].start = PHYS_SDRAM; 233 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 234 return 0; 235 } 236 237 #ifdef CONFIG_RESET_PHY_R 238 void reset_phy(void) 239 { 240 #ifdef CONFIG_DRIVER_DM9000 241 /* 242 * Initialize ethernet HW addr prior to starting Linux, 243 * needed for nfsroot 244 */ 245 eth_init(gd->bd); 246 #endif 247 } 248 #endif 249