1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian@popies.net>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/at91sam9261.h>
12 #include <asm/arch/at91sam9261_matrix.h>
13 #include <asm/arch/at91sam9_smc.h>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91_rstc.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/gpio.h>
18 #include <lcd.h>
19 #include <atmel_lcdc.h>
20 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
21 #include <net.h>
22 #include <netdev.h>
23 #endif
24 
25 DECLARE_GLOBAL_DATA_PTR;
26 
27 /* ------------------------------------------------------------------------- */
28 /*
29  * Miscelaneous platform dependent initialisations
30  */
31 
32 #ifdef CONFIG_CMD_NAND
33 static void at91sam9261ek_nand_hw_init(void)
34 {
35 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
36 	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
37 	unsigned long csa;
38 
39 	/* Enable CS3 */
40 	csa = readl(&matrix->ebicsa);
41 	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
42 
43 	writel(csa, &matrix->ebicsa);
44 
45 	/* Configure SMC CS3 for NAND/SmartMedia */
46 #ifdef CONFIG_AT91SAM9G10EK
47 	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
48 		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
49 		&smc->cs[3].setup);
50 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
51 		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
52 		&smc->cs[3].pulse);
53 	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
54 		&smc->cs[3].cycle);
55 #else
56 	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
57 		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
58 		&smc->cs[3].setup);
59 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
60 		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
61 		&smc->cs[3].pulse);
62 	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
63 		&smc->cs[3].cycle);
64 #endif
65 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
66 		       AT91_SMC_MODE_EXNW_DISABLE |
67 #ifdef CONFIG_SYS_NAND_DBW_16
68 		       AT91_SMC_MODE_DBW_16 |
69 #else /* CONFIG_SYS_NAND_DBW_8 */
70 		       AT91_SMC_MODE_DBW_8 |
71 #endif
72 		       AT91_SMC_MODE_TDF_CYCLE(2),
73 		       &smc->cs[3].mode);
74 
75 	at91_periph_clk_enable(ATMEL_ID_PIOC);
76 
77 	/* Configure RDY/BSY */
78 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
79 
80 	/* Enable NandFlash */
81 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
82 
83 	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
84 	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
85 }
86 #endif
87 
88 #ifdef CONFIG_DRIVER_DM9000
89 static void at91sam9261ek_dm9000_hw_init(void)
90 {
91 	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
92 
93 	/* Configure SMC CS2 for DM9000 */
94 #ifdef CONFIG_AT91SAM9G10EK
95 	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
96 		AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
97 		&smc->cs[2].setup);
98 	writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
99 		AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
100 		&smc->cs[2].pulse);
101 	writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
102 		&smc->cs[2].cycle);
103 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
104 		       AT91_SMC_MODE_EXNW_DISABLE |
105 		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
106 		       AT91_SMC_MODE_TDF_CYCLE(1),
107 		       &smc->cs[2].mode);
108 #else
109 	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
110 		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
111 		&smc->cs[2].setup);
112 	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
113 		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
114 		&smc->cs[2].pulse);
115 	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
116 		&smc->cs[2].cycle);
117 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
118 		       AT91_SMC_MODE_EXNW_DISABLE |
119 		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
120 		       AT91_SMC_MODE_TDF_CYCLE(1),
121 		       &smc->cs[2].mode);
122 #endif
123 
124 	/* Configure Reset signal as output */
125 	at91_set_gpio_output(AT91_PIN_PC10, 0);
126 
127 	/* Configure Interrupt pin as input, no pull-up */
128 	at91_set_gpio_input(AT91_PIN_PC11, 0);
129 }
130 #endif
131 
132 #ifdef CONFIG_LCD
133 vidinfo_t panel_info = {
134 	.vl_col =		240,
135 	.vl_row =		320,
136 	.vl_clk =		4965000,
137 	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
138 				ATMEL_LCDC_INVFRAME_INVERTED,
139 	.vl_bpix =		3,
140 	.vl_tft =		1,
141 	.vl_hsync_len =		5,
142 	.vl_left_margin =	1,
143 	.vl_right_margin =	33,
144 	.vl_vsync_len =		1,
145 	.vl_upper_margin =	1,
146 	.vl_lower_margin =	0,
147 	.mmio =			ATMEL_BASE_LCDC,
148 };
149 
150 void lcd_enable(void)
151 {
152 	at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
153 }
154 
155 void lcd_disable(void)
156 {
157 	at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
158 }
159 
160 static void at91sam9261ek_lcd_hw_init(void)
161 {
162 	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
163 	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
164 	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
165 	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
166 	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
167 	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
168 	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
169 	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
170 	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
171 	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
172 	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
173 	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
174 	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
175 	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
176 	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
177 	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
178 	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
179 	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
180 	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
181 	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
182 	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
183 	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
184 
185 	at91_system_clk_enable(AT91_PMC_HCK1);
186 
187 	/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
188 #ifdef CONFIG_AT91SAM9261EK
189 	gd->fb_base = ATMEL_BASE_SRAM;
190 #endif
191 }
192 
193 #ifdef CONFIG_LCD_INFO
194 #include <nand.h>
195 #include <version.h>
196 
197 void lcd_show_board_info(void)
198 {
199 	ulong dram_size, nand_size;
200 	int i;
201 	char temp[32];
202 
203 	lcd_printf ("%s\n", U_BOOT_VERSION);
204 	lcd_printf ("(C) 2008 ATMEL Corp\n");
205 	lcd_printf ("at91support@atmel.com\n");
206 	lcd_printf ("%s CPU at %s MHz\n",
207 		ATMEL_CPU_NAME,
208 		strmhz(temp, get_cpu_clk_rate()));
209 
210 	dram_size = 0;
211 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
212 		dram_size += gd->bd->bi_dram[i].size;
213 	nand_size = 0;
214 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
215 		nand_size += nand_info[i].size;
216 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
217 		dram_size >> 20,
218 		nand_size >> 20 );
219 }
220 #endif /* CONFIG_LCD_INFO */
221 #endif
222 
223 int board_init(void)
224 {
225 #ifdef CONFIG_AT91SAM9G10EK
226 	/* arch number of AT91SAM9G10EK-Board */
227 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
228 #else
229 	/* arch number of AT91SAM9261EK-Board */
230 	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
231 #endif
232 	/* adress of boot parameters */
233 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
234 
235 	at91_seriald_hw_init();
236 #ifdef CONFIG_CMD_NAND
237 	at91sam9261ek_nand_hw_init();
238 #endif
239 #ifdef CONFIG_HAS_DATAFLASH
240 	at91_spi0_hw_init(1 << 0);
241 #endif
242 #ifdef CONFIG_DRIVER_DM9000
243 	at91sam9261ek_dm9000_hw_init();
244 #endif
245 #ifdef CONFIG_LCD
246 	at91sam9261ek_lcd_hw_init();
247 #endif
248 	return 0;
249 }
250 
251 #ifdef CONFIG_DRIVER_DM9000
252 int board_eth_init(bd_t *bis)
253 {
254 	return dm9000_initialize(bis);
255 }
256 #endif
257 
258 int dram_init(void)
259 {
260 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
261 		CONFIG_SYS_SDRAM_SIZE);
262 
263 	return 0;
264 }
265 
266 #ifdef CONFIG_RESET_PHY_R
267 void reset_phy(void)
268 {
269 #ifdef CONFIG_DRIVER_DM9000
270 	/*
271 	 * Initialize ethernet HW addr prior to starting Linux,
272 	 * needed for nfsroot
273 	 */
274 	eth_init();
275 #endif
276 }
277 #endif
278