1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9261.h> 27 #include <asm/arch/at91sam9261_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_common.h> 30 #include <asm/arch/at91_pmc.h> 31 #include <asm/arch/at91_rstc.h> 32 #include <asm/arch/clk.h> 33 #include <asm/arch/gpio.h> 34 #include <asm/arch/io.h> 35 #include <lcd.h> 36 #include <atmel_lcdc.h> 37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) 38 #include <net.h> 39 #include <netdev.h> 40 #endif 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* ------------------------------------------------------------------------- */ 45 /* 46 * Miscelaneous platform dependent initialisations 47 */ 48 49 #ifdef CONFIG_CMD_NAND 50 static void at91sam9261ek_nand_hw_init(void) 51 { 52 unsigned long csa; 53 54 /* Enable CS3 */ 55 csa = at91_sys_read(AT91_MATRIX_EBICSA); 56 at91_sys_write(AT91_MATRIX_EBICSA, 57 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 58 59 /* Configure SMC CS3 for NAND/SmartMedia */ 60 at91_sys_write(AT91_SMC_SETUP(3), 61 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 62 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 63 at91_sys_write(AT91_SMC_PULSE(3), 64 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 65 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 66 at91_sys_write(AT91_SMC_CYCLE(3), 67 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 68 at91_sys_write(AT91_SMC_MODE(3), 69 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 70 AT91_SMC_EXNWMODE_DISABLE | 71 #ifdef CONFIG_SYS_NAND_DBW_16 72 AT91_SMC_DBW_16 | 73 #else /* CONFIG_SYS_NAND_DBW_8 */ 74 AT91_SMC_DBW_8 | 75 #endif 76 AT91_SMC_TDF_(2)); 77 78 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); 79 80 /* Configure RDY/BSY */ 81 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 82 83 /* Enable NandFlash */ 84 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 85 86 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ 87 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ 88 } 89 #endif 90 91 #ifdef CONFIG_DRIVER_DM9000 92 static void at91sam9261ek_dm9000_hw_init(void) 93 { 94 /* Configure SMC CS2 for DM9000 */ 95 at91_sys_write(AT91_SMC_SETUP(2), 96 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | 97 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); 98 at91_sys_write(AT91_SMC_PULSE(2), 99 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | 100 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); 101 at91_sys_write(AT91_SMC_CYCLE(2), 102 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); 103 at91_sys_write(AT91_SMC_MODE(2), 104 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 105 AT91_SMC_EXNWMODE_DISABLE | 106 AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | 107 AT91_SMC_TDF_(1)); 108 109 /* Configure Reset signal as output */ 110 at91_set_gpio_output(AT91_PIN_PC10, 0); 111 112 /* Configure Interrupt pin as input, no pull-up */ 113 at91_set_gpio_input(AT91_PIN_PC11, 0); 114 } 115 #endif 116 117 #ifdef CONFIG_LCD 118 vidinfo_t panel_info = { 119 vl_col: 240, 120 vl_row: 320, 121 vl_clk: 4965000, 122 vl_sync: ATMEL_LCDC_INVLINE_INVERTED | 123 ATMEL_LCDC_INVFRAME_INVERTED, 124 vl_bpix: 3, 125 vl_tft: 1, 126 vl_hsync_len: 5, 127 vl_left_margin: 1, 128 vl_right_margin:33, 129 vl_vsync_len: 1, 130 vl_upper_margin:1, 131 vl_lower_margin:0, 132 mmio: AT91SAM9261_LCDC_BASE, 133 }; 134 135 void lcd_enable(void) 136 { 137 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */ 138 } 139 140 void lcd_disable(void) 141 { 142 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */ 143 } 144 145 static void at91sam9261ek_lcd_hw_init(void) 146 { 147 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ 148 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ 149 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ 150 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ 151 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ 152 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ 153 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ 154 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ 155 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ 156 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ 157 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ 158 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ 159 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ 160 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ 161 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ 162 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ 163 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ 164 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ 165 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ 166 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ 167 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ 168 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ 169 170 at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); 171 172 gd->fb_base = AT91SAM9261_SRAM_BASE; 173 } 174 175 #ifdef CONFIG_LCD_INFO 176 #include <nand.h> 177 #include <version.h> 178 179 void lcd_show_board_info(void) 180 { 181 ulong dram_size, nand_size; 182 int i; 183 char temp[32]; 184 185 lcd_printf ("%s\n", U_BOOT_VERSION); 186 lcd_printf ("(C) 2008 ATMEL Corp\n"); 187 lcd_printf ("at91support@atmel.com\n"); 188 lcd_printf ("%s CPU at %s MHz\n", 189 AT91_CPU_NAME, 190 strmhz(temp, get_cpu_clk_rate())); 191 192 dram_size = 0; 193 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 194 dram_size += gd->bd->bi_dram[i].size; 195 nand_size = 0; 196 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 197 nand_size += nand_info[i].size; 198 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", 199 dram_size >> 20, 200 nand_size >> 20 ); 201 } 202 #endif /* CONFIG_LCD_INFO */ 203 #endif 204 205 int board_init(void) 206 { 207 /* Enable Ctrlc */ 208 console_init_f(); 209 210 /* arch number of AT91SAM9261EK-Board */ 211 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK; 212 /* adress of boot parameters */ 213 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 214 215 at91_serial_hw_init(); 216 #ifdef CONFIG_CMD_NAND 217 at91sam9261ek_nand_hw_init(); 218 #endif 219 #ifdef CONFIG_HAS_DATAFLASH 220 at91_spi0_hw_init(1 << 0); 221 #endif 222 #ifdef CONFIG_DRIVER_DM9000 223 at91sam9261ek_dm9000_hw_init(); 224 #endif 225 #ifdef CONFIG_LCD 226 at91sam9261ek_lcd_hw_init(); 227 #endif 228 return 0; 229 } 230 231 #ifdef CONFIG_DRIVER_DM9000 232 int board_eth_init(bd_t *bis) 233 { 234 return dm9000_initialize(bis); 235 } 236 #endif 237 int dram_init(void) 238 { 239 gd->bd->bi_dram[0].start = PHYS_SDRAM; 240 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 241 return 0; 242 } 243 244 #ifdef CONFIG_RESET_PHY_R 245 void reset_phy(void) 246 { 247 #ifdef CONFIG_DRIVER_DM9000 248 /* 249 * Initialize ethernet HW addr prior to starting Linux, 250 * needed for nfsroot 251 */ 252 eth_init(gd->bd); 253 #endif 254 } 255 #endif 256