1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9260.h> 27 #include <asm/arch/at91sam9260_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_common.h> 30 #include <asm/arch/at91_pmc.h> 31 #include <asm/arch/at91_rstc.h> 32 #include <asm/arch/gpio.h> 33 #include <asm/arch/io.h> 34 #include <asm/arch/hardware.h> 35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 36 #include <net.h> 37 #endif 38 #include <netdev.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* ------------------------------------------------------------------------- */ 43 /* 44 * Miscelaneous platform dependent initialisations 45 */ 46 47 #ifdef CONFIG_CMD_NAND 48 static void at91sam9260ek_nand_hw_init(void) 49 { 50 unsigned long csa; 51 52 /* Enable CS3 */ 53 csa = at91_sys_read(AT91_MATRIX_EBICSA); 54 at91_sys_write(AT91_MATRIX_EBICSA, 55 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 56 57 /* Configure SMC CS3 for NAND/SmartMedia */ 58 at91_sys_write(AT91_SMC_SETUP(3), 59 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 60 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 61 at91_sys_write(AT91_SMC_PULSE(3), 62 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 63 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 64 at91_sys_write(AT91_SMC_CYCLE(3), 65 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 66 at91_sys_write(AT91_SMC_MODE(3), 67 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 68 AT91_SMC_EXNWMODE_DISABLE | 69 #ifdef CONFIG_SYS_NAND_DBW_16 70 AT91_SMC_DBW_16 | 71 #else /* CONFIG_SYS_NAND_DBW_8 */ 72 AT91_SMC_DBW_8 | 73 #endif 74 AT91_SMC_TDF_(2)); 75 76 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); 77 78 /* Configure RDY/BSY */ 79 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 80 81 /* Enable NandFlash */ 82 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 83 } 84 #endif 85 86 #ifdef CONFIG_MACB 87 static void at91sam9260ek_macb_hw_init(void) 88 { 89 unsigned long rstc; 90 91 /* Enable clock */ 92 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); 93 94 /* 95 * Disable pull-up on: 96 * RXDV (PA17) => PHY normal mode (not Test mode) 97 * ERX0 (PA14) => PHY ADDR0 98 * ERX1 (PA15) => PHY ADDR1 99 * ERX2 (PA25) => PHY ADDR2 100 * ERX3 (PA26) => PHY ADDR3 101 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 102 * 103 * PHY has internal pull-down 104 */ 105 writel(pin_to_mask(AT91_PIN_PA14) | 106 pin_to_mask(AT91_PIN_PA15) | 107 pin_to_mask(AT91_PIN_PA17) | 108 pin_to_mask(AT91_PIN_PA25) | 109 pin_to_mask(AT91_PIN_PA26) | 110 pin_to_mask(AT91_PIN_PA28), 111 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); 112 113 rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; 114 115 /* Need to reset PHY -> 500ms reset */ 116 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 117 (AT91_RSTC_ERSTL & (0x0D << 8)) | 118 AT91_RSTC_URSTEN); 119 120 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); 121 122 /* Wait for end hardware reset */ 123 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); 124 125 /* Restore NRST value */ 126 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 127 (rstc) | 128 AT91_RSTC_URSTEN); 129 130 /* Re-enable pull-up */ 131 writel(pin_to_mask(AT91_PIN_PA14) | 132 pin_to_mask(AT91_PIN_PA15) | 133 pin_to_mask(AT91_PIN_PA17) | 134 pin_to_mask(AT91_PIN_PA25) | 135 pin_to_mask(AT91_PIN_PA26) | 136 pin_to_mask(AT91_PIN_PA28), 137 pin_to_controller(AT91_PIN_PA0) + PIO_PUER); 138 139 at91_macb_hw_init(); 140 } 141 #endif 142 143 int board_init(void) 144 { 145 /* Enable Ctrlc */ 146 console_init_f(); 147 148 #ifdef CONFIG_AT91SAM9G20EK 149 /* arch number of AT91SAM9260EK-Board */ 150 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK; 151 #else 152 /* arch number of AT91SAM9260EK-Board */ 153 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; 154 #endif 155 /* adress of boot parameters */ 156 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 157 158 at91_serial_hw_init(); 159 #ifdef CONFIG_CMD_NAND 160 at91sam9260ek_nand_hw_init(); 161 #endif 162 #ifdef CONFIG_HAS_DATAFLASH 163 at91_spi0_hw_init((1 << 0) | (1 << 1)); 164 #endif 165 #ifdef CONFIG_MACB 166 at91sam9260ek_macb_hw_init(); 167 #endif 168 169 return 0; 170 } 171 172 int dram_init(void) 173 { 174 gd->bd->bi_dram[0].start = PHYS_SDRAM; 175 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 176 return 0; 177 } 178 179 #ifdef CONFIG_RESET_PHY_R 180 void reset_phy(void) 181 { 182 #ifdef CONFIG_MACB 183 /* 184 * Initialize ethernet HW addr prior to starting Linux, 185 * needed for nfsroot 186 */ 187 eth_init(gd->bd); 188 #endif 189 } 190 #endif 191 192 int board_eth_init(bd_t *bis) 193 { 194 int rc = 0; 195 #ifdef CONFIG_MACB 196 rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); 197 #endif 198 return rc; 199 } 200