1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9260.h> 27 #include <asm/arch/at91sam9260_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_pmc.h> 30 #include <asm/arch/at91_rstc.h> 31 #include <asm/arch/gpio.h> 32 #include <asm/arch/io.h> 33 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 34 #include <net.h> 35 #endif 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* ------------------------------------------------------------------------- */ 40 /* 41 * Miscelaneous platform dependent initialisations 42 */ 43 44 static void at91sam9260ek_serial_hw_init(void) 45 { 46 #ifdef CONFIG_USART0 47 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ 48 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ 49 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); 50 #endif 51 52 #ifdef CONFIG_USART1 53 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ 54 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ 55 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); 56 #endif 57 58 #ifdef CONFIG_USART2 59 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ 60 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ 61 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); 62 #endif 63 64 #ifdef CONFIG_USART3 /* DBGU */ 65 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ 66 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ 67 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); 68 #endif 69 } 70 71 #ifdef CONFIG_CMD_NAND 72 static void at91sam9260ek_nand_hw_init(void) 73 { 74 unsigned long csa; 75 76 /* Enable CS3 */ 77 csa = at91_sys_read(AT91_MATRIX_EBICSA); 78 at91_sys_write(AT91_MATRIX_EBICSA, 79 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 80 81 /* Configure SMC CS3 for NAND/SmartMedia */ 82 at91_sys_write(AT91_SMC_SETUP(3), 83 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 84 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 85 at91_sys_write(AT91_SMC_PULSE(3), 86 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 87 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 88 at91_sys_write(AT91_SMC_CYCLE(3), 89 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 90 at91_sys_write(AT91_SMC_MODE(3), 91 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 92 AT91_SMC_EXNWMODE_DISABLE | 93 #ifdef CFG_NAND_DBW_16 94 AT91_SMC_DBW_16 | 95 #else /* CFG_NAND_DBW_8 */ 96 AT91_SMC_DBW_8 | 97 #endif 98 AT91_SMC_TDF_(2)); 99 100 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); 101 102 /* Configure RDY/BSY */ 103 at91_set_gpio_input(AT91_PIN_PC13, 1); 104 105 /* Enable NandFlash */ 106 at91_set_gpio_output(AT91_PIN_PC14, 1); 107 } 108 #endif 109 110 #ifdef CONFIG_HAS_DATAFLASH 111 static void at91sam9260ek_spi_hw_init(void) 112 { 113 at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ 114 at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */ 115 116 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ 117 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ 118 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ 119 120 /* Enable clock */ 121 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); 122 } 123 #endif 124 125 #ifdef CONFIG_MACB 126 static void at91sam9260ek_macb_hw_init(void) 127 { 128 /* Enable clock */ 129 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); 130 131 /* 132 * Disable pull-up on: 133 * RXDV (PA17) => PHY normal mode (not Test mode) 134 * ERX0 (PA14) => PHY ADDR0 135 * ERX1 (PA15) => PHY ADDR1 136 * ERX2 (PA25) => PHY ADDR2 137 * ERX3 (PA26) => PHY ADDR3 138 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 139 * 140 * PHY has internal pull-down 141 */ 142 writel(pin_to_mask(AT91_PIN_PA14) | 143 pin_to_mask(AT91_PIN_PA15) | 144 pin_to_mask(AT91_PIN_PA17) | 145 pin_to_mask(AT91_PIN_PA25) | 146 pin_to_mask(AT91_PIN_PA26) | 147 pin_to_mask(AT91_PIN_PA28), 148 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); 149 150 /* Need to reset PHY -> 500ms reset */ 151 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 152 (AT91_RSTC_ERSTL & (0x0D << 8)) | 153 AT91_RSTC_URSTEN); 154 155 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); 156 157 /* Wait for end hardware reset */ 158 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); 159 160 /* Restore NRST value */ 161 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 162 (AT91_RSTC_ERSTL & (0x0 << 8)) | 163 AT91_RSTC_URSTEN); 164 165 /* Re-enable pull-up */ 166 writel(pin_to_mask(AT91_PIN_PA14) | 167 pin_to_mask(AT91_PIN_PA15) | 168 pin_to_mask(AT91_PIN_PA17) | 169 pin_to_mask(AT91_PIN_PA25) | 170 pin_to_mask(AT91_PIN_PA26) | 171 pin_to_mask(AT91_PIN_PA28), 172 pin_to_controller(AT91_PIN_PA0) + PIO_PUER); 173 174 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ 175 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ 176 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ 177 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ 178 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ 179 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ 180 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ 181 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ 182 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ 183 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ 184 185 #ifndef CONFIG_RMII 186 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ 187 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ 188 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ 189 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ 190 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ 191 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ 192 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ 193 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ 194 #endif 195 196 } 197 #endif 198 199 int board_init(void) 200 { 201 /* Enable Ctrlc */ 202 console_init_f(); 203 204 /* arch number of AT91SAM9260EK-Board */ 205 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; 206 /* adress of boot parameters */ 207 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 208 209 at91sam9260ek_serial_hw_init(); 210 #ifdef CONFIG_CMD_NAND 211 at91sam9260ek_nand_hw_init(); 212 #endif 213 #ifdef CONFIG_HAS_DATAFLASH 214 at91sam9260ek_spi_hw_init(); 215 #endif 216 #ifdef CONFIG_MACB 217 at91sam9260ek_macb_hw_init(); 218 #endif 219 220 return 0; 221 } 222 223 int dram_init(void) 224 { 225 gd->bd->bi_dram[0].start = PHYS_SDRAM; 226 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 227 return 0; 228 } 229 230 #ifdef CONFIG_RESET_PHY_R 231 void reset_phy(void) 232 { 233 #ifdef CONFIG_MACB 234 /* 235 * Initialize ethernet HW addr prior to starting Linux, 236 * needed for nfsroot 237 */ 238 eth_init(gd->bd); 239 #endif 240 } 241 #endif 242