1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9260.h> 27 #include <asm/arch/at91sam9260_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_common.h> 30 #include <asm/arch/at91_pmc.h> 31 #include <asm/arch/at91_rstc.h> 32 #include <asm/arch/gpio.h> 33 #include <asm/arch/io.h> 34 #include <asm/arch/hardware.h> 35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 36 #include <net.h> 37 #endif 38 #include <netdev.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* ------------------------------------------------------------------------- */ 43 /* 44 * Miscelaneous platform dependent initialisations 45 */ 46 47 #ifdef CONFIG_CMD_NAND 48 static void at91sam9260ek_nand_hw_init(void) 49 { 50 unsigned long csa; 51 52 /* Enable CS3 */ 53 csa = at91_sys_read(AT91_MATRIX_EBICSA); 54 at91_sys_write(AT91_MATRIX_EBICSA, 55 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 56 57 /* Configure SMC CS3 for NAND/SmartMedia */ 58 at91_sys_write(AT91_SMC_SETUP(3), 59 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 60 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 61 at91_sys_write(AT91_SMC_PULSE(3), 62 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 63 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 64 at91_sys_write(AT91_SMC_CYCLE(3), 65 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 66 at91_sys_write(AT91_SMC_MODE(3), 67 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 68 AT91_SMC_EXNWMODE_DISABLE | 69 #ifdef CONFIG_SYS_NAND_DBW_16 70 AT91_SMC_DBW_16 | 71 #else /* CONFIG_SYS_NAND_DBW_8 */ 72 AT91_SMC_DBW_8 | 73 #endif 74 AT91_SMC_TDF_(2)); 75 76 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); 77 78 /* Configure RDY/BSY */ 79 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 80 81 /* Enable NandFlash */ 82 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 83 } 84 #endif 85 86 #ifdef CONFIG_MACB 87 static void at91sam9260ek_macb_hw_init(void) 88 { 89 /* Enable clock */ 90 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); 91 92 /* 93 * Disable pull-up on: 94 * RXDV (PA17) => PHY normal mode (not Test mode) 95 * ERX0 (PA14) => PHY ADDR0 96 * ERX1 (PA15) => PHY ADDR1 97 * ERX2 (PA25) => PHY ADDR2 98 * ERX3 (PA26) => PHY ADDR3 99 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 100 * 101 * PHY has internal pull-down 102 */ 103 writel(pin_to_mask(AT91_PIN_PA14) | 104 pin_to_mask(AT91_PIN_PA15) | 105 pin_to_mask(AT91_PIN_PA17) | 106 pin_to_mask(AT91_PIN_PA25) | 107 pin_to_mask(AT91_PIN_PA26) | 108 pin_to_mask(AT91_PIN_PA28), 109 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); 110 111 /* Need to reset PHY -> 500ms reset */ 112 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 113 (AT91_RSTC_ERSTL & (0x0D << 8)) | 114 AT91_RSTC_URSTEN); 115 116 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); 117 118 /* Wait for end hardware reset */ 119 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); 120 121 /* Restore NRST value */ 122 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 123 (AT91_RSTC_ERSTL & (0x0 << 8)) | 124 AT91_RSTC_URSTEN); 125 126 /* Re-enable pull-up */ 127 writel(pin_to_mask(AT91_PIN_PA14) | 128 pin_to_mask(AT91_PIN_PA15) | 129 pin_to_mask(AT91_PIN_PA17) | 130 pin_to_mask(AT91_PIN_PA25) | 131 pin_to_mask(AT91_PIN_PA26) | 132 pin_to_mask(AT91_PIN_PA28), 133 pin_to_controller(AT91_PIN_PA0) + PIO_PUER); 134 135 at91_macb_hw_init(); 136 } 137 #endif 138 139 int board_init(void) 140 { 141 /* Enable Ctrlc */ 142 console_init_f(); 143 144 #ifdef CONFIG_AT91SAM9G20EK 145 /* arch number of AT91SAM9260EK-Board */ 146 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK; 147 #else 148 /* arch number of AT91SAM9260EK-Board */ 149 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; 150 #endif 151 /* adress of boot parameters */ 152 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 153 154 at91_serial_hw_init(); 155 #ifdef CONFIG_CMD_NAND 156 at91sam9260ek_nand_hw_init(); 157 #endif 158 #ifdef CONFIG_HAS_DATAFLASH 159 at91_spi0_hw_init((1 << 0) || (1 << 1)); 160 #endif 161 #ifdef CONFIG_MACB 162 at91sam9260ek_macb_hw_init(); 163 #endif 164 165 return 0; 166 } 167 168 int dram_init(void) 169 { 170 gd->bd->bi_dram[0].start = PHYS_SDRAM; 171 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 172 return 0; 173 } 174 175 #ifdef CONFIG_RESET_PHY_R 176 void reset_phy(void) 177 { 178 #ifdef CONFIG_MACB 179 /* 180 * Initialize ethernet HW addr prior to starting Linux, 181 * needed for nfsroot 182 */ 183 eth_init(gd->bd); 184 #endif 185 } 186 #endif 187 188 int board_eth_init(bd_t *bis) 189 { 190 int rc = 0; 191 #ifdef CONFIG_MACB 192 rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); 193 #endif 194 return rc; 195 } 196