1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9260.h> 27 #include <asm/arch/at91sam9260_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_pmc.h> 30 #include <asm/arch/at91_rstc.h> 31 #include <asm/arch/gpio.h> 32 #include <asm/arch/io.h> 33 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 34 #include <net.h> 35 #endif 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* ------------------------------------------------------------------------- */ 40 /* 41 * Miscelaneous platform dependent initialisations 42 */ 43 44 static void at91sam9260ek_serial_hw_init(void) 45 { 46 #ifdef CONFIG_USART0 47 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ 48 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ 49 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); 50 #endif 51 52 #ifdef CONFIG_USART1 53 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ 54 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ 55 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); 56 #endif 57 58 #ifdef CONFIG_USART2 59 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ 60 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ 61 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); 62 #endif 63 64 #ifdef CONFIG_USART3 /* DBGU */ 65 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ 66 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ 67 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); 68 #endif 69 } 70 71 #ifdef CONFIG_CMD_NAND 72 static void at91sam9260ek_nand_hw_init(void) 73 { 74 unsigned long csa; 75 76 /* Enable CS3 */ 77 csa = at91_sys_read(AT91_MATRIX_EBICSA); 78 at91_sys_write(AT91_MATRIX_EBICSA, 79 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 80 81 /* Configure SMC CS3 for NAND/SmartMedia */ 82 at91_sys_write(AT91_SMC_SETUP(3), 83 AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | 84 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 85 at91_sys_write(AT91_SMC_PULSE(3), 86 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 87 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 88 at91_sys_write(AT91_SMC_CYCLE(3), 89 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 90 at91_sys_write(AT91_SMC_MODE(3), 91 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 92 AT91_SMC_EXNWMODE_DISABLE | 93 AT91_SMC_DBW_8 | AT91_SMC_TDF_(2)); 94 95 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); 96 97 /* Configure RDY/BSY */ 98 at91_set_gpio_input(AT91_PIN_PC13, 1); 99 100 /* Enable NandFlash */ 101 at91_set_gpio_output(AT91_PIN_PC14, 1); 102 } 103 #endif 104 105 #ifdef CONFIG_HAS_DATAFLASH 106 static void at91sam9260ek_spi_hw_init(void) 107 { 108 at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ 109 at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */ 110 111 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ 112 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ 113 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ 114 115 /* Enable clock */ 116 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); 117 } 118 #endif 119 120 #ifdef CONFIG_MACB 121 static void at91sam9260ek_macb_hw_init(void) 122 { 123 /* Enable clock */ 124 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); 125 126 /* 127 * Disable pull-up on: 128 * RXDV (PA17) => PHY normal mode (not Test mode) 129 * ERX0 (PA14) => PHY ADDR0 130 * ERX1 (PA15) => PHY ADDR1 131 * ERX2 (PA25) => PHY ADDR2 132 * ERX3 (PA26) => PHY ADDR3 133 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 134 * 135 * PHY has internal pull-down 136 */ 137 writel(pin_to_mask(AT91_PIN_PA14) | 138 pin_to_mask(AT91_PIN_PA15) | 139 pin_to_mask(AT91_PIN_PA17) | 140 pin_to_mask(AT91_PIN_PA25) | 141 pin_to_mask(AT91_PIN_PA26) | 142 pin_to_mask(AT91_PIN_PA28), 143 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); 144 145 /* Need to reset PHY -> 500ms reset */ 146 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 147 AT91_RSTC_ERSTL | (0x0D << 8) | 148 AT91_RSTC_URSTEN); 149 150 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); 151 152 /* Wait for end hardware reset */ 153 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); 154 155 /* Restore NRST value */ 156 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 157 AT91_RSTC_ERSTL | (0x0 << 8) | 158 AT91_RSTC_URSTEN); 159 160 /* Re-enable pull-up */ 161 writel(pin_to_mask(AT91_PIN_PA14) | 162 pin_to_mask(AT91_PIN_PA15) | 163 pin_to_mask(AT91_PIN_PA17) | 164 pin_to_mask(AT91_PIN_PA25) | 165 pin_to_mask(AT91_PIN_PA26) | 166 pin_to_mask(AT91_PIN_PA28), 167 pin_to_controller(AT91_PIN_PA0) + PIO_PUER); 168 169 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ 170 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ 171 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ 172 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ 173 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ 174 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ 175 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ 176 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ 177 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ 178 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ 179 180 #ifndef CONFIG_RMII 181 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ 182 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ 183 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ 184 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ 185 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ 186 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ 187 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ 188 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ 189 #endif 190 191 } 192 #endif 193 194 int board_init(void) 195 { 196 /* Enable Ctrlc */ 197 console_init_f(); 198 199 /* arch number of AT91SAM9260EK-Board */ 200 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; 201 /* adress of boot parameters */ 202 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 203 204 at91sam9260ek_serial_hw_init(); 205 #ifdef CONFIG_CMD_NAND 206 at91sam9260ek_nand_hw_init(); 207 #endif 208 #ifdef CONFIG_HAS_DATAFLASH 209 at91sam9260ek_spi_hw_init(); 210 #endif 211 #ifdef CONFIG_MACB 212 at91sam9260ek_macb_hw_init(); 213 #endif 214 215 return 0; 216 } 217 218 int dram_init(void) 219 { 220 gd->bd->bi_dram[0].start = PHYS_SDRAM; 221 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 222 return 0; 223 } 224 225 #ifdef CONFIG_RESET_PHY_R 226 void reset_phy(void) 227 { 228 #ifdef CONFIG_MACB 229 /* 230 * Initialize ethernet HW addr prior to starting Linux, 231 * needed for nfsroot 232 */ 233 eth_init(gd->bd); 234 #endif 235 } 236 #endif 237