1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian.pop@leadtechdesign.com> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/arch/at91sam9260.h> 27 #include <asm/arch/at91sam9260_matrix.h> 28 #include <asm/arch/at91sam9_smc.h> 29 #include <asm/arch/at91_common.h> 30 #include <asm/arch/at91_pmc.h> 31 #include <asm/arch/at91_rstc.h> 32 #include <asm/arch/gpio.h> 33 #include <asm/arch/io.h> 34 #include <asm/arch/hardware.h> 35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 36 #include <net.h> 37 #endif 38 #include <netdev.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 /* ------------------------------------------------------------------------- */ 43 /* 44 * Miscelaneous platform dependent initialisations 45 */ 46 47 #ifdef CONFIG_CMD_NAND 48 static void at91sam9260ek_nand_hw_init(void) 49 { 50 unsigned long csa; 51 52 /* Enable CS3 */ 53 csa = at91_sys_read(AT91_MATRIX_EBICSA); 54 at91_sys_write(AT91_MATRIX_EBICSA, 55 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 56 57 /* Configure SMC CS3 for NAND/SmartMedia */ 58 at91_sys_write(AT91_SMC_SETUP(3), 59 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | 60 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); 61 at91_sys_write(AT91_SMC_PULSE(3), 62 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 63 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 64 at91_sys_write(AT91_SMC_CYCLE(3), 65 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 66 at91_sys_write(AT91_SMC_MODE(3), 67 AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 68 AT91_SMC_EXNWMODE_DISABLE | 69 #ifdef CONFIG_SYS_NAND_DBW_16 70 AT91_SMC_DBW_16 | 71 #else /* CONFIG_SYS_NAND_DBW_8 */ 72 AT91_SMC_DBW_8 | 73 #endif 74 AT91_SMC_TDF_(2)); 75 76 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); 77 78 /* Configure RDY/BSY */ 79 at91_set_gpio_input(AT91_PIN_PC13, 1); 80 81 /* Enable NandFlash */ 82 at91_set_gpio_output(AT91_PIN_PC14, 1); 83 } 84 #endif 85 86 #ifdef CONFIG_HAS_DATAFLASH 87 static void at91sam9260ek_spi_hw_init(void) 88 { 89 at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ 90 at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */ 91 92 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ 93 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ 94 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ 95 96 /* Enable clock */ 97 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); 98 } 99 #endif 100 101 #ifdef CONFIG_MACB 102 static void at91sam9260ek_macb_hw_init(void) 103 { 104 /* Enable clock */ 105 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); 106 107 /* 108 * Disable pull-up on: 109 * RXDV (PA17) => PHY normal mode (not Test mode) 110 * ERX0 (PA14) => PHY ADDR0 111 * ERX1 (PA15) => PHY ADDR1 112 * ERX2 (PA25) => PHY ADDR2 113 * ERX3 (PA26) => PHY ADDR3 114 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 115 * 116 * PHY has internal pull-down 117 */ 118 writel(pin_to_mask(AT91_PIN_PA14) | 119 pin_to_mask(AT91_PIN_PA15) | 120 pin_to_mask(AT91_PIN_PA17) | 121 pin_to_mask(AT91_PIN_PA25) | 122 pin_to_mask(AT91_PIN_PA26) | 123 pin_to_mask(AT91_PIN_PA28), 124 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); 125 126 /* Need to reset PHY -> 500ms reset */ 127 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 128 (AT91_RSTC_ERSTL & (0x0D << 8)) | 129 AT91_RSTC_URSTEN); 130 131 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); 132 133 /* Wait for end hardware reset */ 134 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); 135 136 /* Restore NRST value */ 137 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 138 (AT91_RSTC_ERSTL & (0x0 << 8)) | 139 AT91_RSTC_URSTEN); 140 141 /* Re-enable pull-up */ 142 writel(pin_to_mask(AT91_PIN_PA14) | 143 pin_to_mask(AT91_PIN_PA15) | 144 pin_to_mask(AT91_PIN_PA17) | 145 pin_to_mask(AT91_PIN_PA25) | 146 pin_to_mask(AT91_PIN_PA26) | 147 pin_to_mask(AT91_PIN_PA28), 148 pin_to_controller(AT91_PIN_PA0) + PIO_PUER); 149 150 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ 151 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ 152 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ 153 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ 154 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ 155 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ 156 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ 157 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ 158 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ 159 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ 160 161 #ifndef CONFIG_RMII 162 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ 163 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ 164 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ 165 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ 166 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ 167 #if defined(CONFIG_AT91SAM9260EK) 168 /* 169 * use PA10, PA11 for ETX2, ETX3. 170 * PA23 and PA24 are for TWI EEPROM 171 */ 172 at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */ 173 at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */ 174 #else 175 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ 176 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ 177 #endif 178 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ 179 #endif 180 181 } 182 #endif 183 184 int board_init(void) 185 { 186 /* Enable Ctrlc */ 187 console_init_f(); 188 189 /* arch number of AT91SAM9260EK-Board */ 190 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; 191 /* adress of boot parameters */ 192 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 193 194 at91_serial_hw_init(); 195 #ifdef CONFIG_CMD_NAND 196 at91sam9260ek_nand_hw_init(); 197 #endif 198 #ifdef CONFIG_HAS_DATAFLASH 199 at91sam9260ek_spi_hw_init(); 200 #endif 201 #ifdef CONFIG_MACB 202 at91sam9260ek_macb_hw_init(); 203 #endif 204 205 return 0; 206 } 207 208 int dram_init(void) 209 { 210 gd->bd->bi_dram[0].start = PHYS_SDRAM; 211 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 212 return 0; 213 } 214 215 #ifdef CONFIG_RESET_PHY_R 216 void reset_phy(void) 217 { 218 #ifdef CONFIG_MACB 219 /* 220 * Initialize ethernet HW addr prior to starting Linux, 221 * needed for nfsroot 222 */ 223 eth_init(gd->bd); 224 #endif 225 } 226 #endif 227 228 int board_eth_init(bd_t *bis) 229 { 230 int rc = 0; 231 #ifdef CONFIG_MACB 232 rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); 233 #endif 234 return rc; 235 } 236