10176d43eSStelian Pop /* 20176d43eSStelian Pop * (C) Copyright 2007-2008 3567fb852SStelian Pop * Stelian Pop <stelian.pop@leadtechdesign.com> 40176d43eSStelian Pop * Lead Tech Design <www.leadtechdesign.com> 50176d43eSStelian Pop * 60176d43eSStelian Pop * See file CREDITS for list of people who contributed to this 70176d43eSStelian Pop * project. 80176d43eSStelian Pop * 90176d43eSStelian Pop * This program is free software; you can redistribute it and/or 100176d43eSStelian Pop * modify it under the terms of the GNU General Public License as 110176d43eSStelian Pop * published by the Free Software Foundation; either version 2 of 120176d43eSStelian Pop * the License, or (at your option) any later version. 130176d43eSStelian Pop * 140176d43eSStelian Pop * This program is distributed in the hope that it will be useful, 150176d43eSStelian Pop * but WITHOUT ANY WARRANTY; without even the implied warranty of 160176d43eSStelian Pop * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 170176d43eSStelian Pop * GNU General Public License for more details. 180176d43eSStelian Pop * 190176d43eSStelian Pop * You should have received a copy of the GNU General Public License 200176d43eSStelian Pop * along with this program; if not, write to the Free Software 210176d43eSStelian Pop * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 220176d43eSStelian Pop * MA 02111-1307 USA 230176d43eSStelian Pop */ 240176d43eSStelian Pop 250176d43eSStelian Pop #include <common.h> 260176d43eSStelian Pop #include <asm/arch/at91sam9260.h> 270176d43eSStelian Pop #include <asm/arch/at91sam9260_matrix.h> 284f6c8101SStelian Pop #include <asm/arch/at91sam9_smc.h> 290176d43eSStelian Pop #include <asm/arch/at91_pmc.h> 300176d43eSStelian Pop #include <asm/arch/at91_rstc.h> 310176d43eSStelian Pop #include <asm/arch/gpio.h> 320176d43eSStelian Pop #include <asm/arch/io.h> 330176d43eSStelian Pop #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) 340176d43eSStelian Pop #include <net.h> 350176d43eSStelian Pop #endif 360176d43eSStelian Pop 370176d43eSStelian Pop DECLARE_GLOBAL_DATA_PTR; 380176d43eSStelian Pop 390176d43eSStelian Pop /* ------------------------------------------------------------------------- */ 400176d43eSStelian Pop /* 410176d43eSStelian Pop * Miscelaneous platform dependent initialisations 420176d43eSStelian Pop */ 430176d43eSStelian Pop 440176d43eSStelian Pop static void at91sam9260ek_serial_hw_init(void) 450176d43eSStelian Pop { 460176d43eSStelian Pop #ifdef CONFIG_USART0 470176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ 480176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ 490176d43eSStelian Pop at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); 500176d43eSStelian Pop #endif 510176d43eSStelian Pop 520176d43eSStelian Pop #ifdef CONFIG_USART1 530176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ 540176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ 550176d43eSStelian Pop at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); 560176d43eSStelian Pop #endif 570176d43eSStelian Pop 580176d43eSStelian Pop #ifdef CONFIG_USART2 590176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ 600176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ 610176d43eSStelian Pop at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); 620176d43eSStelian Pop #endif 630176d43eSStelian Pop 640176d43eSStelian Pop #ifdef CONFIG_USART3 /* DBGU */ 650176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ 660176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ 670176d43eSStelian Pop at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); 680176d43eSStelian Pop #endif 690176d43eSStelian Pop } 700176d43eSStelian Pop 710176d43eSStelian Pop #ifdef CONFIG_CMD_NAND 720176d43eSStelian Pop static void at91sam9260ek_nand_hw_init(void) 730176d43eSStelian Pop { 740176d43eSStelian Pop unsigned long csa; 750176d43eSStelian Pop 760176d43eSStelian Pop /* Enable CS3 */ 770176d43eSStelian Pop csa = at91_sys_read(AT91_MATRIX_EBICSA); 780176d43eSStelian Pop at91_sys_write(AT91_MATRIX_EBICSA, 790176d43eSStelian Pop csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 800176d43eSStelian Pop 810176d43eSStelian Pop /* Configure SMC CS3 for NAND/SmartMedia */ 820176d43eSStelian Pop at91_sys_write(AT91_SMC_SETUP(3), 830176d43eSStelian Pop AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | 840176d43eSStelian Pop AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 850176d43eSStelian Pop at91_sys_write(AT91_SMC_PULSE(3), 860176d43eSStelian Pop AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | 870176d43eSStelian Pop AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 880176d43eSStelian Pop at91_sys_write(AT91_SMC_CYCLE(3), 890176d43eSStelian Pop AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 900176d43eSStelian Pop at91_sys_write(AT91_SMC_MODE(3), 910176d43eSStelian Pop AT91_SMC_READMODE | AT91_SMC_WRITEMODE | 920176d43eSStelian Pop AT91_SMC_EXNWMODE_DISABLE | 93*c1212b2fSStelian Pop #ifdef CFG_NAND_DBW_16 94*c1212b2fSStelian Pop AT91_SMC_DBW_16 | 95*c1212b2fSStelian Pop #else /* CFG_NAND_DBW_8 */ 96*c1212b2fSStelian Pop AT91_SMC_DBW_8 | 97*c1212b2fSStelian Pop #endif 98*c1212b2fSStelian Pop AT91_SMC_TDF_(2)); 990176d43eSStelian Pop 1000176d43eSStelian Pop at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); 1010176d43eSStelian Pop 1020176d43eSStelian Pop /* Configure RDY/BSY */ 1030176d43eSStelian Pop at91_set_gpio_input(AT91_PIN_PC13, 1); 1040176d43eSStelian Pop 1050176d43eSStelian Pop /* Enable NandFlash */ 1060176d43eSStelian Pop at91_set_gpio_output(AT91_PIN_PC14, 1); 1070176d43eSStelian Pop } 1080176d43eSStelian Pop #endif 1090176d43eSStelian Pop 1100176d43eSStelian Pop #ifdef CONFIG_HAS_DATAFLASH 1110176d43eSStelian Pop static void at91sam9260ek_spi_hw_init(void) 1120176d43eSStelian Pop { 1130176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ 1140176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */ 1150176d43eSStelian Pop 1160176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ 1170176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ 1180176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ 1190176d43eSStelian Pop 1200176d43eSStelian Pop /* Enable clock */ 1210176d43eSStelian Pop at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); 1220176d43eSStelian Pop } 1230176d43eSStelian Pop #endif 1240176d43eSStelian Pop 1250176d43eSStelian Pop #ifdef CONFIG_MACB 1260176d43eSStelian Pop static void at91sam9260ek_macb_hw_init(void) 1270176d43eSStelian Pop { 1280176d43eSStelian Pop /* Enable clock */ 1290176d43eSStelian Pop at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); 1300176d43eSStelian Pop 1310176d43eSStelian Pop /* 1320176d43eSStelian Pop * Disable pull-up on: 1330176d43eSStelian Pop * RXDV (PA17) => PHY normal mode (not Test mode) 1340176d43eSStelian Pop * ERX0 (PA14) => PHY ADDR0 1350176d43eSStelian Pop * ERX1 (PA15) => PHY ADDR1 1360176d43eSStelian Pop * ERX2 (PA25) => PHY ADDR2 1370176d43eSStelian Pop * ERX3 (PA26) => PHY ADDR3 1380176d43eSStelian Pop * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 1390176d43eSStelian Pop * 1400176d43eSStelian Pop * PHY has internal pull-down 1410176d43eSStelian Pop */ 1420176d43eSStelian Pop writel(pin_to_mask(AT91_PIN_PA14) | 1430176d43eSStelian Pop pin_to_mask(AT91_PIN_PA15) | 1440176d43eSStelian Pop pin_to_mask(AT91_PIN_PA17) | 1450176d43eSStelian Pop pin_to_mask(AT91_PIN_PA25) | 1460176d43eSStelian Pop pin_to_mask(AT91_PIN_PA26) | 1470176d43eSStelian Pop pin_to_mask(AT91_PIN_PA28), 1480176d43eSStelian Pop pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); 1490176d43eSStelian Pop 1500176d43eSStelian Pop /* Need to reset PHY -> 500ms reset */ 1510176d43eSStelian Pop at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 1520176d43eSStelian Pop AT91_RSTC_ERSTL | (0x0D << 8) | 1530176d43eSStelian Pop AT91_RSTC_URSTEN); 1540176d43eSStelian Pop 1550176d43eSStelian Pop at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); 1560176d43eSStelian Pop 1570176d43eSStelian Pop /* Wait for end hardware reset */ 1580176d43eSStelian Pop while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); 1590176d43eSStelian Pop 1600176d43eSStelian Pop /* Restore NRST value */ 1610176d43eSStelian Pop at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | 1620176d43eSStelian Pop AT91_RSTC_ERSTL | (0x0 << 8) | 1630176d43eSStelian Pop AT91_RSTC_URSTEN); 1640176d43eSStelian Pop 1650176d43eSStelian Pop /* Re-enable pull-up */ 1660176d43eSStelian Pop writel(pin_to_mask(AT91_PIN_PA14) | 1670176d43eSStelian Pop pin_to_mask(AT91_PIN_PA15) | 1680176d43eSStelian Pop pin_to_mask(AT91_PIN_PA17) | 1690176d43eSStelian Pop pin_to_mask(AT91_PIN_PA25) | 1700176d43eSStelian Pop pin_to_mask(AT91_PIN_PA26) | 1710176d43eSStelian Pop pin_to_mask(AT91_PIN_PA28), 1720176d43eSStelian Pop pin_to_controller(AT91_PIN_PA0) + PIO_PUER); 1730176d43eSStelian Pop 1740176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ 1750176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ 1760176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ 1770176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ 1780176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ 1790176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ 1800176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ 1810176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ 1820176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ 1830176d43eSStelian Pop at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ 1840176d43eSStelian Pop 1850176d43eSStelian Pop #ifndef CONFIG_RMII 1860176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ 1870176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ 1880176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ 1890176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ 1900176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ 1910176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ 1920176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ 1930176d43eSStelian Pop at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ 1940176d43eSStelian Pop #endif 1950176d43eSStelian Pop 1960176d43eSStelian Pop } 1970176d43eSStelian Pop #endif 1980176d43eSStelian Pop 1990176d43eSStelian Pop int board_init(void) 2000176d43eSStelian Pop { 2010176d43eSStelian Pop /* Enable Ctrlc */ 2020176d43eSStelian Pop console_init_f(); 2030176d43eSStelian Pop 2040176d43eSStelian Pop /* arch number of AT91SAM9260EK-Board */ 2050176d43eSStelian Pop gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK; 2060176d43eSStelian Pop /* adress of boot parameters */ 2070176d43eSStelian Pop gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 2080176d43eSStelian Pop 2090176d43eSStelian Pop at91sam9260ek_serial_hw_init(); 2100176d43eSStelian Pop #ifdef CONFIG_CMD_NAND 2110176d43eSStelian Pop at91sam9260ek_nand_hw_init(); 2120176d43eSStelian Pop #endif 2130176d43eSStelian Pop #ifdef CONFIG_HAS_DATAFLASH 2140176d43eSStelian Pop at91sam9260ek_spi_hw_init(); 2150176d43eSStelian Pop #endif 2160176d43eSStelian Pop #ifdef CONFIG_MACB 2170176d43eSStelian Pop at91sam9260ek_macb_hw_init(); 2180176d43eSStelian Pop #endif 2190176d43eSStelian Pop 2200176d43eSStelian Pop return 0; 2210176d43eSStelian Pop } 2220176d43eSStelian Pop 2230176d43eSStelian Pop int dram_init(void) 2240176d43eSStelian Pop { 2250176d43eSStelian Pop gd->bd->bi_dram[0].start = PHYS_SDRAM; 2260176d43eSStelian Pop gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; 2270176d43eSStelian Pop return 0; 2280176d43eSStelian Pop } 2290176d43eSStelian Pop 2300176d43eSStelian Pop #ifdef CONFIG_RESET_PHY_R 2310176d43eSStelian Pop void reset_phy(void) 2320176d43eSStelian Pop { 2330176d43eSStelian Pop #ifdef CONFIG_MACB 2340176d43eSStelian Pop /* 2350176d43eSStelian Pop * Initialize ethernet HW addr prior to starting Linux, 2360176d43eSStelian Pop * needed for nfsroot 2370176d43eSStelian Pop */ 2380176d43eSStelian Pop eth_init(gd->bd); 2390176d43eSStelian Pop #endif 2400176d43eSStelian Pop } 2410176d43eSStelian Pop #endif 242