1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l 6 */ 7 8 #include <common.h> 9 #include <watchdog.h> 10 #include <command.h> 11 #include <asm/m5329.h> 12 #include <asm/immap_5329.h> 13 #include <asm/io.h> 14 15 /* needed for astro bus: */ 16 #include <asm/uart.h> 17 #include "astro.h" 18 19 DECLARE_GLOBAL_DATA_PTR; 20 extern void uart_port_conf(void); 21 22 int checkboard(void) 23 { 24 puts("Board: "); 25 puts("ASTRO MCF5373L (Urmel) Board\n"); 26 return 0; 27 } 28 29 int dram_init(void) 30 { 31 #if !defined(CONFIG_MONITOR_IS_IN_RAM) 32 sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); 33 34 /* 35 * GPIO configuration for bus should be set correctly from reset, 36 * so we do not care! First, set up address space: at this point, 37 * we should be running from internal SRAM; 38 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, 39 * and do not care where it is 40 */ 41 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, 42 &sdp->cs0); 43 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, 44 &sdp->cs1); 45 /* 46 * I am not sure from the data sheet, but it seems burst length 47 * has to be 8 for the 16 bit data bus we use; 48 * so these values are for BL = 8 49 */ 50 __raw_writel(0x33211530, &sdp->cfg1); 51 __raw_writel(0x56570000, &sdp->cfg2); 52 /* send PrechargeALL, REF and IREF remain cleared! */ 53 __raw_writel(0xE1462C02, &sdp->ctrl); 54 udelay(1); 55 /* refresh SDRAM twice */ 56 __raw_writel(0xE1462C04, &sdp->ctrl); 57 udelay(1); 58 __raw_writel(0xE1462C04, &sdp->ctrl); 59 /* init MR */ 60 __raw_writel(0x008D0000, &sdp->mode); 61 /* initialize EMR */ 62 __raw_writel(0x80010000, &sdp->mode); 63 /* wait until DLL is locked */ 64 udelay(1); 65 /* 66 * enable automatic refresh, lock mode register, 67 * clear iref and ipall 68 */ 69 __raw_writel(0x71462C00, &sdp->ctrl); 70 /* Dummy write to start SDRAM */ 71 writel(0, CONFIG_SYS_SDRAM_BASE); 72 #endif 73 74 /* 75 * for get_ram_size() to work, both CS areas have to be 76 * configured, i.e. CS1 has to be explicitely disabled, else 77 * probing for memory will cause the SDRAM bus to hang! 78 * (Do not rely on the SDCS register(s) being set to 0x00000000 79 * during reset as stated in the data sheet.) 80 */ 81 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 82 0x80000000 - CONFIG_SYS_SDRAM_BASE); 83 84 return 0; 85 } 86 87 #define UART_BASE MMAP_UART0 88 int rs_serial_init(int port, int baud) 89 { 90 uart_t *uart; 91 u32 counter; 92 93 switch (port) { 94 case 0: 95 uart = (uart_t *)(MMAP_UART0); 96 break; 97 case 1: 98 uart = (uart_t *)(MMAP_UART1); 99 break; 100 case 2: 101 uart = (uart_t *)(MMAP_UART2); 102 break; 103 default: 104 uart = (uart_t *)(MMAP_UART0); 105 } 106 107 uart_port_conf(); 108 109 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ 110 writeb(UART_UCR_RESET_RX, &uart->ucr); 111 writeb(UART_UCR_RESET_TX, &uart->ucr); 112 writeb(UART_UCR_RESET_ERROR, &uart->ucr); 113 writeb(UART_UCR_RESET_MR, &uart->ucr); 114 __asm__ ("nop"); 115 116 writeb(0, &uart->uimr); 117 118 /* write to CSR: RX/TX baud rate from timers */ 119 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); 120 121 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); 122 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); 123 124 /* Setting up BaudRate */ 125 counter = (u32) (gd->bus_clk / (baud)); 126 counter >>= 5; 127 128 /* write to CTUR: divide counter upper byte */ 129 writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); 130 /* write to CTLR: divide counter lower byte */ 131 writeb((u8) (counter & 0x00ff), &uart->ubg2); 132 133 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); 134 135 return 0; 136 } 137 138 void astro_put_char(char ch) 139 { 140 uart_t *uart; 141 unsigned long timer; 142 143 uart = (uart_t *)(MMAP_UART0); 144 /* 145 * Wait for last character to go. Timeout of 6ms should 146 * be enough for our lowest baud rate of 2400. 147 */ 148 timer = get_timer(0); 149 while (get_timer(timer) < 6) { 150 if (readb(&uart->usr) & UART_USR_TXRDY) 151 break; 152 } 153 writeb(ch, &uart->utb); 154 155 return; 156 } 157 158 int astro_is_char(void) 159 { 160 uart_t *uart; 161 162 uart = (uart_t *)(MMAP_UART0); 163 return readb(&uart->usr) & UART_USR_RXRDY; 164 } 165 166 int astro_get_char(void) 167 { 168 uart_t *uart; 169 170 uart = (uart_t *)(MMAP_UART0); 171 while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; 172 return readb(&uart->urb); 173 } 174 175 int misc_init_r(void) 176 { 177 int retval = 0; 178 179 puts("Configure Xilinx FPGA..."); 180 retval = astro5373l_xilinx_load(); 181 if (!retval) { 182 puts("failed!\n"); 183 return retval; 184 } 185 puts("done\n"); 186 187 puts("Configure Altera FPGA..."); 188 retval = astro5373l_altera_load(); 189 if (!retval) { 190 puts("failed!\n"); 191 return retval; 192 } 193 puts("done\n"); 194 195 return retval; 196 } 197