1 /* 2 * (C) Copyright 2000-2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <watchdog.h> 27 #include <command.h> 28 #include <asm/m5329.h> 29 #include <asm/immap_5329.h> 30 #include <asm/io.h> 31 32 /* needed for astro bus: */ 33 #include <asm/uart.h> 34 #include "astro.h" 35 36 DECLARE_GLOBAL_DATA_PTR; 37 extern void uart_port_conf(void); 38 39 int checkboard(void) 40 { 41 puts("Board: "); 42 puts("ASTRO MCF5373L (Urmel) Board\n"); 43 return 0; 44 } 45 46 phys_size_t initdram(int board_type) 47 { 48 #if !defined(CONFIG_MONITOR_IS_IN_RAM) 49 sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); 50 51 /* 52 * GPIO configuration for bus should be set correctly from reset, 53 * so we do not care! First, set up address space: at this point, 54 * we should be running from internal SRAM; 55 * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM, 56 * and do not care where it is 57 */ 58 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, 59 &sdp->cs0); 60 __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, 61 &sdp->cs1); 62 /* 63 * I am not sure from the data sheet, but it seems burst length 64 * has to be 8 for the 16 bit data bus we use; 65 * so these values are for BL = 8 66 */ 67 __raw_writel(0x33211530, &sdp->cfg1); 68 __raw_writel(0x56570000, &sdp->cfg2); 69 /* send PrechargeALL, REF and IREF remain cleared! */ 70 __raw_writel(0xE1462C02, &sdp->ctrl); 71 udelay(1); 72 /* refresh SDRAM twice */ 73 __raw_writel(0xE1462C04, &sdp->ctrl); 74 udelay(1); 75 __raw_writel(0xE1462C04, &sdp->ctrl); 76 /* init MR */ 77 __raw_writel(0x008D0000, &sdp->mode); 78 /* initialize EMR */ 79 __raw_writel(0x80010000, &sdp->mode); 80 /* wait until DLL is locked */ 81 udelay(1); 82 /* 83 * enable automatic refresh, lock mode register, 84 * clear iref and ipall 85 */ 86 __raw_writel(0x71462C00, &sdp->ctrl); 87 /* Dummy write to start SDRAM */ 88 writel(0, CONFIG_SYS_SDRAM_BASE); 89 #endif 90 91 /* 92 * for get_ram_size() to work, both CS areas have to be 93 * configured, i.e. CS1 has to be explicitely disabled, else 94 * probing for memory will cause the SDRAM bus to hang! 95 * (Do not rely on the SDCS register(s) being set to 0x00000000 96 * during reset as stated in the data sheet.) 97 */ 98 return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE, 99 0x80000000 - CONFIG_SYS_SDRAM_BASE); 100 } 101 102 #define UART_BASE MMAP_UART0 103 int rs_serial_init(int port, int baud) 104 { 105 uart_t *uart; 106 u32 counter; 107 108 switch (port) { 109 case 0: 110 uart = (uart_t *)(MMAP_UART0); 111 break; 112 case 1: 113 uart = (uart_t *)(MMAP_UART1); 114 break; 115 case 2: 116 uart = (uart_t *)(MMAP_UART2); 117 break; 118 default: 119 uart = (uart_t *)(MMAP_UART0); 120 } 121 122 uart_port_conf(); 123 124 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ 125 writeb(UART_UCR_RESET_RX, &uart->ucr); 126 writeb(UART_UCR_RESET_TX, &uart->ucr); 127 writeb(UART_UCR_RESET_ERROR, &uart->ucr); 128 writeb(UART_UCR_RESET_MR, &uart->ucr); 129 __asm__ ("nop"); 130 131 writeb(0, &uart->uimr); 132 133 /* write to CSR: RX/TX baud rate from timers */ 134 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); 135 136 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); 137 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); 138 139 /* Setting up BaudRate */ 140 counter = (u32) (gd->bus_clk / (baud)); 141 counter >>= 5; 142 143 /* write to CTUR: divide counter upper byte */ 144 writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); 145 /* write to CTLR: divide counter lower byte */ 146 writeb((u8) (counter & 0x00ff), &uart->ubg2); 147 148 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); 149 150 return 0; 151 } 152 153 void astro_put_char(char ch) 154 { 155 uart_t *uart; 156 unsigned long timer; 157 158 uart = (uart_t *)(MMAP_UART0); 159 /* 160 * Wait for last character to go. Timeout of 6ms should 161 * be enough for our lowest baud rate of 2400. 162 */ 163 timer = get_timer(0); 164 while (get_timer(timer) < 6) { 165 if (readb(&uart->usr) & UART_USR_TXRDY) 166 break; 167 } 168 writeb(ch, &uart->utb); 169 170 return; 171 } 172 173 int astro_is_char(void) 174 { 175 uart_t *uart; 176 177 uart = (uart_t *)(MMAP_UART0); 178 return readb(&uart->usr) & UART_USR_RXRDY; 179 } 180 181 int astro_get_char(void) 182 { 183 uart_t *uart; 184 185 uart = (uart_t *)(MMAP_UART0); 186 while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; 187 return readb(&uart->urb); 188 } 189 190 int misc_init_r(void) 191 { 192 int retval = 0; 193 194 puts("Configure Xilinx FPGA..."); 195 retval = astro5373l_xilinx_load(); 196 if (!retval) { 197 puts("failed!\n"); 198 return retval; 199 } 200 puts("done\n"); 201 202 puts("Configure Altera FPGA..."); 203 retval = astro5373l_altera_load(); 204 if (!retval) { 205 puts("failed!\n"); 206 return retval; 207 } 208 puts("done\n"); 209 210 return retval; 211 } 212