1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 #include <common.h> 6 #include <asm/io.h> 7 8 #define SCU_BASE 0x1e6e2000 9 10 #define AST_LPC_BASE 0x1e789000 11 #define HICR5 0x80 12 #define HICR6 0x84 13 #define SNPWADR 0x90 14 #define HICRB 0x100 15 #define LPC_SNOOP_ADDR 0x80 16 17 #define AST_GPIO_BASE 0x1e780000 18 19 /* HICR5 Bits */ 20 #define HICR5_EN_SIOGIO (1 << 31) /* Enable SIOGIO */ 21 #define HICR5_EN80HGIO (1 << 30) /* Enable 80hGIO */ 22 #define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */ 23 #define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */ 24 #define HICR5_UNKVAL_MASK 0x1FFF0000 /* Bits with unknown values on reset */ 25 #define HICR5_ENINT_SNP0W (1 << 1) /* Enable Snooping address 0 */ 26 #define HICR5_EN_SNP0W (1 << 0) /* Enable Snooping address 0 */ 27 28 /* HRCR6 Bits */ 29 #define HICR6_STR_SNP0W (1 << 0) /* Interrupt Status Snoop address 0 */ 30 #define HICR6_STR_SNP1W (1 << 1) /* Interrupt Status Snoop address 1 */ 31 32 /* HICRB Bits */ 33 #define HICRB_EN80HSGIO (1 << 13) /* Enable 80hSGIO */ 34 35 static void __maybe_unused port80h_snoop_init(void) 36 { 37 uint32_t value; 38 /* enable port80h snoop and sgpio */ 39 /* set lpc snoop #0 to port 0x80 */ 40 value = readl(AST_LPC_BASE + SNPWADR) & 0xffff0000; 41 writel(value | LPC_SNOOP_ADDR, AST_LPC_BASE + SNPWADR); 42 43 /* clear interrupt status */ 44 value = readl(AST_LPC_BASE + HICR6); 45 value |= HICR6_STR_SNP0W | HICR6_STR_SNP1W; 46 writel(value, AST_LPC_BASE + HICR6); 47 48 /* enable lpc snoop #0 and SIOGIO */ 49 value = readl(AST_LPC_BASE + HICR5) & ~(HICR5_UNKVAL_MASK); 50 value |= HICR5_EN_SIOGIO | HICR5_EN_SNP0W; 51 writel(value, AST_LPC_BASE + HICR5); 52 53 /* enable port80h snoop on SGPIO */ 54 value = readl(AST_LPC_BASE + HICRB) | HICRB_EN80HSGIO; 55 writel(value, AST_LPC_BASE + HICRB); 56 } 57 58 static void __maybe_unused sgpio_init(void) 59 { 60 #define SGPIO_CLK_DIV(N) ((N) << 16) 61 #define SGPIO_BYTES(N) ((N) << 6) 62 #define SGPIO_ENABLE 1 63 #define GPIO554 0x554 64 #define SCU_414 0x414 /* Multi-function Pin Control #5 */ 65 #define SCU_414_SGPM_MASK GENMASK(27, 24) 66 67 uint32_t value; 68 /* set the sgpio clock to pclk/(2*(5+1)) or ~2 MHz */ 69 value = SGPIO_CLK_DIV(256) | SGPIO_BYTES(10) | SGPIO_ENABLE; 70 writel(value, AST_GPIO_BASE + GPIO554); 71 writel(readl(SCU_BASE | SCU_414) | SCU_414_SGPM_MASK, 72 SCU_BASE | SCU_414); 73 } 74 75 int board_early_init_f(void) 76 { 77 #if 0 78 port80h_snoop_init(); 79 sgpio_init(); 80 #endif 81 return 0; 82 } 83