1 /*
2  *  arch/arm/include/asm/hardware/pci_v3.h
3  *
4  *  Internal header file PCI V3 chip
5  *
6  *  Copyright (C) ARM Limited
7  *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
22  */
23 #ifndef ASM_ARM_HARDWARE_PCI_V3_H
24 #define ASM_ARM_HARDWARE_PCI_V3_H
25 
26 /* -------------------------------------------------------------------------------
27  *  V3 Local Bus to PCI Bridge definitions
28  * -------------------------------------------------------------------------------
29  *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
30  *  All V3 register names are prefaced by V3_ to avoid clashing with any other
31  *  PCI definitions.  Their names match the user's manual.
32  *
33  *  I'm assuming that I20 is disabled.
34  *
35  */
36 #define V3_PCI_VENDOR                   0x00000000
37 #define V3_PCI_DEVICE                   0x00000002
38 #define V3_PCI_CMD                      0x00000004
39 #define V3_PCI_STAT                     0x00000006
40 #define V3_PCI_CC_REV                   0x00000008
41 #define V3_PCI_HDR_CFG                  0x0000000C
42 #define V3_PCI_IO_BASE                  0x00000010
43 #define V3_PCI_BASE0                    0x00000014
44 #define V3_PCI_BASE1                    0x00000018
45 #define V3_PCI_SUB_VENDOR               0x0000002C
46 #define V3_PCI_SUB_ID                   0x0000002E
47 #define V3_PCI_ROM                      0x00000030
48 #define V3_PCI_BPARAM                   0x0000003C
49 #define V3_PCI_MAP0                     0x00000040
50 #define V3_PCI_MAP1                     0x00000044
51 #define V3_PCI_INT_STAT                 0x00000048
52 #define V3_PCI_INT_CFG                  0x0000004C
53 #define V3_LB_BASE0                     0x00000054
54 #define V3_LB_BASE1                     0x00000058
55 #define V3_LB_MAP0                      0x0000005E
56 #define V3_LB_MAP1                      0x00000062
57 #define V3_LB_BASE2                     0x00000064
58 #define V3_LB_MAP2                      0x00000066
59 #define V3_LB_SIZE                      0x00000068
60 #define V3_LB_IO_BASE                   0x0000006E
61 #define V3_FIFO_CFG                     0x00000070
62 #define V3_FIFO_PRIORITY                0x00000072
63 #define V3_FIFO_STAT                    0x00000074
64 #define V3_LB_ISTAT                     0x00000076
65 #define V3_LB_IMASK                     0x00000077
66 #define V3_SYSTEM                       0x00000078
67 #define V3_LB_CFG                       0x0000007A
68 #define V3_PCI_CFG                      0x0000007C
69 #define V3_DMA_PCI_ADR0                 0x00000080
70 #define V3_DMA_PCI_ADR1                 0x00000090
71 #define V3_DMA_LOCAL_ADR0               0x00000084
72 #define V3_DMA_LOCAL_ADR1               0x00000094
73 #define V3_DMA_LENGTH0                  0x00000088
74 #define V3_DMA_LENGTH1                  0x00000098
75 #define V3_DMA_CSR0                     0x0000008B
76 #define V3_DMA_CSR1                     0x0000009B
77 #define V3_DMA_CTLB_ADR0                0x0000008C
78 #define V3_DMA_CTLB_ADR1                0x0000009C
79 #define V3_DMA_DELAY                    0x000000E0
80 #define V3_MAIL_DATA                    0x000000C0
81 #define V3_PCI_MAIL_IEWR                0x000000D0
82 #define V3_PCI_MAIL_IERD                0x000000D2
83 #define V3_LB_MAIL_IEWR                 0x000000D4
84 #define V3_LB_MAIL_IERD                 0x000000D6
85 #define V3_MAIL_WR_STAT                 0x000000D8
86 #define V3_MAIL_RD_STAT                 0x000000DA
87 #define V3_QBA_MAP                      0x000000DC
88 
89 /*  PCI COMMAND REGISTER bits
90  */
91 #define V3_COMMAND_M_FBB_EN             (1 << 9)
92 #define V3_COMMAND_M_SERR_EN            (1 << 8)
93 #define V3_COMMAND_M_PAR_EN             (1 << 6)
94 #define V3_COMMAND_M_MASTER_EN          (1 << 2)
95 #define V3_COMMAND_M_MEM_EN             (1 << 1)
96 #define V3_COMMAND_M_IO_EN              (1 << 0)
97 
98 /*  SYSTEM REGISTER bits
99  */
100 #define V3_SYSTEM_M_RST_OUT             (1 << 15)
101 #define V3_SYSTEM_M_LOCK                (1 << 14)
102 
103 /*  PCI_CFG bits
104  */
105 #define V3_PCI_CFG_M_I2O_EN		(1 << 15)
106 #define V3_PCI_CFG_M_IO_REG_DIS		(1 << 14)
107 #define V3_PCI_CFG_M_IO_DIS		(1 << 13)
108 #define V3_PCI_CFG_M_EN3V		(1 << 12)
109 #define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
110 #define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
111 #define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
112 
113 /*  PCI_BASE register bits (PCI -> Local Bus)
114  */
115 #define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
116 #define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
117 #define V3_PCI_BASE_M_PREFETCH          (1 << 3)
118 #define V3_PCI_BASE_M_TYPE              (3 << 1)
119 #define V3_PCI_BASE_M_IO                (1 << 0)
120 
121 /*  PCI MAP register bits (PCI -> Local bus)
122  */
123 #define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
124 #define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
125 #define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
126 #define V3_PCI_MAP_M_SWAP               (3 << 8)
127 #define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
128 #define V3_PCI_MAP_M_REG_EN             (1 << 1)
129 #define V3_PCI_MAP_M_ENABLE             (1 << 0)
130 
131 #define V3_PCI_MAP_M_ADR_SIZE_1MB	(0 << 4)
132 #define V3_PCI_MAP_M_ADR_SIZE_2MB	(1 << 4)
133 #define V3_PCI_MAP_M_ADR_SIZE_4MB	(2 << 4)
134 #define V3_PCI_MAP_M_ADR_SIZE_8MB	(3 << 4)
135 #define V3_PCI_MAP_M_ADR_SIZE_16MB	(4 << 4)
136 #define V3_PCI_MAP_M_ADR_SIZE_32MB	(5 << 4)
137 #define V3_PCI_MAP_M_ADR_SIZE_64MB	(6 << 4)
138 #define V3_PCI_MAP_M_ADR_SIZE_128MB	(7 << 4)
139 #define V3_PCI_MAP_M_ADR_SIZE_256MB	(8 << 4)
140 #define V3_PCI_MAP_M_ADR_SIZE_512MB	(9 << 4)
141 #define V3_PCI_MAP_M_ADR_SIZE_1GB	(10 << 4)
142 #define V3_PCI_MAP_M_ADR_SIZE_2GB	(11 << 4)
143 
144 /*
145  *  LB_BASE0,1 register bits (Local bus -> PCI)
146  */
147 #define V3_LB_BASE_ADR_BASE		0xfff00000
148 #define V3_LB_BASE_SWAP			(3 << 8)
149 #define V3_LB_BASE_ADR_SIZE		(15 << 4)
150 #define V3_LB_BASE_PREFETCH		(1 << 3)
151 #define V3_LB_BASE_ENABLE		(1 << 0)
152 
153 #define V3_LB_BASE_ADR_SIZE_1MB		(0 << 4)
154 #define V3_LB_BASE_ADR_SIZE_2MB		(1 << 4)
155 #define V3_LB_BASE_ADR_SIZE_4MB		(2 << 4)
156 #define V3_LB_BASE_ADR_SIZE_8MB		(3 << 4)
157 #define V3_LB_BASE_ADR_SIZE_16MB	(4 << 4)
158 #define V3_LB_BASE_ADR_SIZE_32MB	(5 << 4)
159 #define V3_LB_BASE_ADR_SIZE_64MB	(6 << 4)
160 #define V3_LB_BASE_ADR_SIZE_128MB	(7 << 4)
161 #define V3_LB_BASE_ADR_SIZE_256MB	(8 << 4)
162 #define V3_LB_BASE_ADR_SIZE_512MB	(9 << 4)
163 #define V3_LB_BASE_ADR_SIZE_1GB		(10 << 4)
164 #define V3_LB_BASE_ADR_SIZE_2GB		(11 << 4)
165 
166 #define v3_addr_to_lb_base(a)	((a) & V3_LB_BASE_ADR_BASE)
167 
168 /*
169  *  LB_MAP0,1 register bits (Local bus -> PCI)
170  */
171 #define V3_LB_MAP_MAP_ADR		0xfff0
172 #define V3_LB_MAP_TYPE			(7 << 1)
173 #define V3_LB_MAP_AD_LOW_EN		(1 << 0)
174 
175 #define V3_LB_MAP_TYPE_IACK		(0 << 1)
176 #define V3_LB_MAP_TYPE_IO		(1 << 1)
177 #define V3_LB_MAP_TYPE_MEM		(3 << 1)
178 #define V3_LB_MAP_TYPE_CONFIG		(5 << 1)
179 #define V3_LB_MAP_TYPE_MEM_MULTIPLE	(6 << 1)
180 
181 /* PCI MAP register bits (PCI -> Local bus) */
182 #define v3_addr_to_lb_map(a)	(((a) >> 16) & V3_LB_MAP_MAP_ADR)
183 
184 /*
185  *  LB_BASE2 register bits (Local bus -> PCI IO)
186  */
187 #define V3_LB_BASE2_ADR_BASE		0xff00
188 #define V3_LB_BASE2_SWAP		(3 << 6)
189 #define V3_LB_BASE2_ENABLE		(1 << 0)
190 
191 #define v3_addr_to_lb_base2(a)	(((a) >> 16) & V3_LB_BASE2_ADR_BASE)
192 
193 /*
194  *  LB_MAP2 register bits (Local bus -> PCI IO)
195  */
196 #define V3_LB_MAP2_MAP_ADR		0xff00
197 
198 #define v3_addr_to_lb_map2(a)	(((a) >> 16) & V3_LB_MAP2_MAP_ADR)
199 
200 #endif
201