1 /*
2  *  arch/arm/include/asm/hardware/pci_v3.h
3  *
4  *  Internal header file PCI V3 chip
5  *
6  *  Copyright (C) ARM Limited
7  *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 #ifndef ASM_ARM_HARDWARE_PCI_V3_H
12 #define ASM_ARM_HARDWARE_PCI_V3_H
13 
14 /* -------------------------------------------------------------------------------
15  *  V3 Local Bus to PCI Bridge definitions
16  * -------------------------------------------------------------------------------
17  *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
18  *  All V3 register names are prefaced by V3_ to avoid clashing with any other
19  *  PCI definitions.  Their names match the user's manual.
20  *
21  *  I'm assuming that I20 is disabled.
22  *
23  */
24 #define V3_PCI_VENDOR                   0x00000000
25 #define V3_PCI_DEVICE                   0x00000002
26 #define V3_PCI_CMD                      0x00000004
27 #define V3_PCI_STAT                     0x00000006
28 #define V3_PCI_CC_REV                   0x00000008
29 #define V3_PCI_HDR_CFG                  0x0000000C
30 #define V3_PCI_IO_BASE                  0x00000010
31 #define V3_PCI_BASE0                    0x00000014
32 #define V3_PCI_BASE1                    0x00000018
33 #define V3_PCI_SUB_VENDOR               0x0000002C
34 #define V3_PCI_SUB_ID                   0x0000002E
35 #define V3_PCI_ROM                      0x00000030
36 #define V3_PCI_BPARAM                   0x0000003C
37 #define V3_PCI_MAP0                     0x00000040
38 #define V3_PCI_MAP1                     0x00000044
39 #define V3_PCI_INT_STAT                 0x00000048
40 #define V3_PCI_INT_CFG                  0x0000004C
41 #define V3_LB_BASE0                     0x00000054
42 #define V3_LB_BASE1                     0x00000058
43 #define V3_LB_MAP0                      0x0000005E
44 #define V3_LB_MAP1                      0x00000062
45 #define V3_LB_BASE2                     0x00000064
46 #define V3_LB_MAP2                      0x00000066
47 #define V3_LB_SIZE                      0x00000068
48 #define V3_LB_IO_BASE                   0x0000006E
49 #define V3_FIFO_CFG                     0x00000070
50 #define V3_FIFO_PRIORITY                0x00000072
51 #define V3_FIFO_STAT                    0x00000074
52 #define V3_LB_ISTAT                     0x00000076
53 #define V3_LB_IMASK                     0x00000077
54 #define V3_SYSTEM                       0x00000078
55 #define V3_LB_CFG                       0x0000007A
56 #define V3_PCI_CFG                      0x0000007C
57 #define V3_DMA_PCI_ADR0                 0x00000080
58 #define V3_DMA_PCI_ADR1                 0x00000090
59 #define V3_DMA_LOCAL_ADR0               0x00000084
60 #define V3_DMA_LOCAL_ADR1               0x00000094
61 #define V3_DMA_LENGTH0                  0x00000088
62 #define V3_DMA_LENGTH1                  0x00000098
63 #define V3_DMA_CSR0                     0x0000008B
64 #define V3_DMA_CSR1                     0x0000009B
65 #define V3_DMA_CTLB_ADR0                0x0000008C
66 #define V3_DMA_CTLB_ADR1                0x0000009C
67 #define V3_DMA_DELAY                    0x000000E0
68 #define V3_MAIL_DATA                    0x000000C0
69 #define V3_PCI_MAIL_IEWR                0x000000D0
70 #define V3_PCI_MAIL_IERD                0x000000D2
71 #define V3_LB_MAIL_IEWR                 0x000000D4
72 #define V3_LB_MAIL_IERD                 0x000000D6
73 #define V3_MAIL_WR_STAT                 0x000000D8
74 #define V3_MAIL_RD_STAT                 0x000000DA
75 #define V3_QBA_MAP                      0x000000DC
76 
77 /*  PCI COMMAND REGISTER bits
78  */
79 #define V3_COMMAND_M_FBB_EN             (1 << 9)
80 #define V3_COMMAND_M_SERR_EN            (1 << 8)
81 #define V3_COMMAND_M_PAR_EN             (1 << 6)
82 #define V3_COMMAND_M_MASTER_EN          (1 << 2)
83 #define V3_COMMAND_M_MEM_EN             (1 << 1)
84 #define V3_COMMAND_M_IO_EN              (1 << 0)
85 
86 /*  SYSTEM REGISTER bits
87  */
88 #define V3_SYSTEM_M_RST_OUT             (1 << 15)
89 #define V3_SYSTEM_M_LOCK                (1 << 14)
90 
91 /*  PCI_CFG bits
92  */
93 #define V3_PCI_CFG_M_I2O_EN		(1 << 15)
94 #define V3_PCI_CFG_M_IO_REG_DIS		(1 << 14)
95 #define V3_PCI_CFG_M_IO_DIS		(1 << 13)
96 #define V3_PCI_CFG_M_EN3V		(1 << 12)
97 #define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
98 #define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
99 #define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
100 
101 /*  PCI_BASE register bits (PCI -> Local Bus)
102  */
103 #define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
104 #define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
105 #define V3_PCI_BASE_M_PREFETCH          (1 << 3)
106 #define V3_PCI_BASE_M_TYPE              (3 << 1)
107 #define V3_PCI_BASE_M_IO                (1 << 0)
108 
109 /*  PCI MAP register bits (PCI -> Local bus)
110  */
111 #define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
112 #define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
113 #define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
114 #define V3_PCI_MAP_M_SWAP               (3 << 8)
115 #define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
116 #define V3_PCI_MAP_M_REG_EN             (1 << 1)
117 #define V3_PCI_MAP_M_ENABLE             (1 << 0)
118 
119 #define V3_PCI_MAP_M_ADR_SIZE_1MB	(0 << 4)
120 #define V3_PCI_MAP_M_ADR_SIZE_2MB	(1 << 4)
121 #define V3_PCI_MAP_M_ADR_SIZE_4MB	(2 << 4)
122 #define V3_PCI_MAP_M_ADR_SIZE_8MB	(3 << 4)
123 #define V3_PCI_MAP_M_ADR_SIZE_16MB	(4 << 4)
124 #define V3_PCI_MAP_M_ADR_SIZE_32MB	(5 << 4)
125 #define V3_PCI_MAP_M_ADR_SIZE_64MB	(6 << 4)
126 #define V3_PCI_MAP_M_ADR_SIZE_128MB	(7 << 4)
127 #define V3_PCI_MAP_M_ADR_SIZE_256MB	(8 << 4)
128 #define V3_PCI_MAP_M_ADR_SIZE_512MB	(9 << 4)
129 #define V3_PCI_MAP_M_ADR_SIZE_1GB	(10 << 4)
130 #define V3_PCI_MAP_M_ADR_SIZE_2GB	(11 << 4)
131 
132 /*
133  *  LB_BASE0,1 register bits (Local bus -> PCI)
134  */
135 #define V3_LB_BASE_ADR_BASE		0xfff00000
136 #define V3_LB_BASE_SWAP			(3 << 8)
137 #define V3_LB_BASE_ADR_SIZE		(15 << 4)
138 #define V3_LB_BASE_PREFETCH		(1 << 3)
139 #define V3_LB_BASE_ENABLE		(1 << 0)
140 
141 #define V3_LB_BASE_ADR_SIZE_1MB		(0 << 4)
142 #define V3_LB_BASE_ADR_SIZE_2MB		(1 << 4)
143 #define V3_LB_BASE_ADR_SIZE_4MB		(2 << 4)
144 #define V3_LB_BASE_ADR_SIZE_8MB		(3 << 4)
145 #define V3_LB_BASE_ADR_SIZE_16MB	(4 << 4)
146 #define V3_LB_BASE_ADR_SIZE_32MB	(5 << 4)
147 #define V3_LB_BASE_ADR_SIZE_64MB	(6 << 4)
148 #define V3_LB_BASE_ADR_SIZE_128MB	(7 << 4)
149 #define V3_LB_BASE_ADR_SIZE_256MB	(8 << 4)
150 #define V3_LB_BASE_ADR_SIZE_512MB	(9 << 4)
151 #define V3_LB_BASE_ADR_SIZE_1GB		(10 << 4)
152 #define V3_LB_BASE_ADR_SIZE_2GB		(11 << 4)
153 
154 #define v3_addr_to_lb_base(a)	((a) & V3_LB_BASE_ADR_BASE)
155 
156 /*
157  *  LB_MAP0,1 register bits (Local bus -> PCI)
158  */
159 #define V3_LB_MAP_MAP_ADR		0xfff0
160 #define V3_LB_MAP_TYPE			(7 << 1)
161 #define V3_LB_MAP_AD_LOW_EN		(1 << 0)
162 
163 #define V3_LB_MAP_TYPE_IACK		(0 << 1)
164 #define V3_LB_MAP_TYPE_IO		(1 << 1)
165 #define V3_LB_MAP_TYPE_MEM		(3 << 1)
166 #define V3_LB_MAP_TYPE_CONFIG		(5 << 1)
167 #define V3_LB_MAP_TYPE_MEM_MULTIPLE	(6 << 1)
168 
169 /* PCI MAP register bits (PCI -> Local bus) */
170 #define v3_addr_to_lb_map(a)	(((a) >> 16) & V3_LB_MAP_MAP_ADR)
171 
172 /*
173  *  LB_BASE2 register bits (Local bus -> PCI IO)
174  */
175 #define V3_LB_BASE2_ADR_BASE		0xff00
176 #define V3_LB_BASE2_SWAP		(3 << 6)
177 #define V3_LB_BASE2_ENABLE		(1 << 0)
178 
179 #define v3_addr_to_lb_base2(a)	(((a) >> 16) & V3_LB_BASE2_ADR_BASE)
180 
181 /*
182  *  LB_MAP2 register bits (Local bus -> PCI IO)
183  */
184 #define V3_LB_MAP2_MAP_ADR		0xff00
185 
186 #define v3_addr_to_lb_map2(a)	(((a) >> 16) & V3_LB_MAP2_MAP_ADR)
187 
188 #endif
189