1*2458716aSLinus Walleij /* 2*2458716aSLinus Walleij * arch/arm/include/asm/hardware/pci_v3.h 3*2458716aSLinus Walleij * 4*2458716aSLinus Walleij * Internal header file PCI V3 chip 5*2458716aSLinus Walleij * 6*2458716aSLinus Walleij * Copyright (C) ARM Limited 7*2458716aSLinus Walleij * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. 8*2458716aSLinus Walleij * 9*2458716aSLinus Walleij * This program is free software; you can redistribute it and/or modify 10*2458716aSLinus Walleij * it under the terms of the GNU General Public License as published by 11*2458716aSLinus Walleij * the Free Software Foundation; either version 2 of the License, or 12*2458716aSLinus Walleij * (at your option) any later version. 13*2458716aSLinus Walleij * 14*2458716aSLinus Walleij * This program is distributed in the hope that it will be useful, 15*2458716aSLinus Walleij * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*2458716aSLinus Walleij * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*2458716aSLinus Walleij * GNU General Public License for more details. 18*2458716aSLinus Walleij * 19*2458716aSLinus Walleij * You should have received a copy of the GNU General Public License 20*2458716aSLinus Walleij * along with this program; if not, write to the Free Software 21*2458716aSLinus Walleij * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22*2458716aSLinus Walleij */ 23*2458716aSLinus Walleij #ifndef ASM_ARM_HARDWARE_PCI_V3_H 24*2458716aSLinus Walleij #define ASM_ARM_HARDWARE_PCI_V3_H 25*2458716aSLinus Walleij 26*2458716aSLinus Walleij /* ------------------------------------------------------------------------------- 27*2458716aSLinus Walleij * V3 Local Bus to PCI Bridge definitions 28*2458716aSLinus Walleij * ------------------------------------------------------------------------------- 29*2458716aSLinus Walleij * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 30*2458716aSLinus Walleij * All V3 register names are prefaced by V3_ to avoid clashing with any other 31*2458716aSLinus Walleij * PCI definitions. Their names match the user's manual. 32*2458716aSLinus Walleij * 33*2458716aSLinus Walleij * I'm assuming that I20 is disabled. 34*2458716aSLinus Walleij * 35*2458716aSLinus Walleij */ 36*2458716aSLinus Walleij #define V3_PCI_VENDOR 0x00000000 37*2458716aSLinus Walleij #define V3_PCI_DEVICE 0x00000002 38*2458716aSLinus Walleij #define V3_PCI_CMD 0x00000004 39*2458716aSLinus Walleij #define V3_PCI_STAT 0x00000006 40*2458716aSLinus Walleij #define V3_PCI_CC_REV 0x00000008 41*2458716aSLinus Walleij #define V3_PCI_HDR_CFG 0x0000000C 42*2458716aSLinus Walleij #define V3_PCI_IO_BASE 0x00000010 43*2458716aSLinus Walleij #define V3_PCI_BASE0 0x00000014 44*2458716aSLinus Walleij #define V3_PCI_BASE1 0x00000018 45*2458716aSLinus Walleij #define V3_PCI_SUB_VENDOR 0x0000002C 46*2458716aSLinus Walleij #define V3_PCI_SUB_ID 0x0000002E 47*2458716aSLinus Walleij #define V3_PCI_ROM 0x00000030 48*2458716aSLinus Walleij #define V3_PCI_BPARAM 0x0000003C 49*2458716aSLinus Walleij #define V3_PCI_MAP0 0x00000040 50*2458716aSLinus Walleij #define V3_PCI_MAP1 0x00000044 51*2458716aSLinus Walleij #define V3_PCI_INT_STAT 0x00000048 52*2458716aSLinus Walleij #define V3_PCI_INT_CFG 0x0000004C 53*2458716aSLinus Walleij #define V3_LB_BASE0 0x00000054 54*2458716aSLinus Walleij #define V3_LB_BASE1 0x00000058 55*2458716aSLinus Walleij #define V3_LB_MAP0 0x0000005E 56*2458716aSLinus Walleij #define V3_LB_MAP1 0x00000062 57*2458716aSLinus Walleij #define V3_LB_BASE2 0x00000064 58*2458716aSLinus Walleij #define V3_LB_MAP2 0x00000066 59*2458716aSLinus Walleij #define V3_LB_SIZE 0x00000068 60*2458716aSLinus Walleij #define V3_LB_IO_BASE 0x0000006E 61*2458716aSLinus Walleij #define V3_FIFO_CFG 0x00000070 62*2458716aSLinus Walleij #define V3_FIFO_PRIORITY 0x00000072 63*2458716aSLinus Walleij #define V3_FIFO_STAT 0x00000074 64*2458716aSLinus Walleij #define V3_LB_ISTAT 0x00000076 65*2458716aSLinus Walleij #define V3_LB_IMASK 0x00000077 66*2458716aSLinus Walleij #define V3_SYSTEM 0x00000078 67*2458716aSLinus Walleij #define V3_LB_CFG 0x0000007A 68*2458716aSLinus Walleij #define V3_PCI_CFG 0x0000007C 69*2458716aSLinus Walleij #define V3_DMA_PCI_ADR0 0x00000080 70*2458716aSLinus Walleij #define V3_DMA_PCI_ADR1 0x00000090 71*2458716aSLinus Walleij #define V3_DMA_LOCAL_ADR0 0x00000084 72*2458716aSLinus Walleij #define V3_DMA_LOCAL_ADR1 0x00000094 73*2458716aSLinus Walleij #define V3_DMA_LENGTH0 0x00000088 74*2458716aSLinus Walleij #define V3_DMA_LENGTH1 0x00000098 75*2458716aSLinus Walleij #define V3_DMA_CSR0 0x0000008B 76*2458716aSLinus Walleij #define V3_DMA_CSR1 0x0000009B 77*2458716aSLinus Walleij #define V3_DMA_CTLB_ADR0 0x0000008C 78*2458716aSLinus Walleij #define V3_DMA_CTLB_ADR1 0x0000009C 79*2458716aSLinus Walleij #define V3_DMA_DELAY 0x000000E0 80*2458716aSLinus Walleij #define V3_MAIL_DATA 0x000000C0 81*2458716aSLinus Walleij #define V3_PCI_MAIL_IEWR 0x000000D0 82*2458716aSLinus Walleij #define V3_PCI_MAIL_IERD 0x000000D2 83*2458716aSLinus Walleij #define V3_LB_MAIL_IEWR 0x000000D4 84*2458716aSLinus Walleij #define V3_LB_MAIL_IERD 0x000000D6 85*2458716aSLinus Walleij #define V3_MAIL_WR_STAT 0x000000D8 86*2458716aSLinus Walleij #define V3_MAIL_RD_STAT 0x000000DA 87*2458716aSLinus Walleij #define V3_QBA_MAP 0x000000DC 88*2458716aSLinus Walleij 89*2458716aSLinus Walleij /* PCI COMMAND REGISTER bits 90*2458716aSLinus Walleij */ 91*2458716aSLinus Walleij #define V3_COMMAND_M_FBB_EN (1 << 9) 92*2458716aSLinus Walleij #define V3_COMMAND_M_SERR_EN (1 << 8) 93*2458716aSLinus Walleij #define V3_COMMAND_M_PAR_EN (1 << 6) 94*2458716aSLinus Walleij #define V3_COMMAND_M_MASTER_EN (1 << 2) 95*2458716aSLinus Walleij #define V3_COMMAND_M_MEM_EN (1 << 1) 96*2458716aSLinus Walleij #define V3_COMMAND_M_IO_EN (1 << 0) 97*2458716aSLinus Walleij 98*2458716aSLinus Walleij /* SYSTEM REGISTER bits 99*2458716aSLinus Walleij */ 100*2458716aSLinus Walleij #define V3_SYSTEM_M_RST_OUT (1 << 15) 101*2458716aSLinus Walleij #define V3_SYSTEM_M_LOCK (1 << 14) 102*2458716aSLinus Walleij 103*2458716aSLinus Walleij /* PCI_CFG bits 104*2458716aSLinus Walleij */ 105*2458716aSLinus Walleij #define V3_PCI_CFG_M_I2O_EN (1 << 15) 106*2458716aSLinus Walleij #define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) 107*2458716aSLinus Walleij #define V3_PCI_CFG_M_IO_DIS (1 << 13) 108*2458716aSLinus Walleij #define V3_PCI_CFG_M_EN3V (1 << 12) 109*2458716aSLinus Walleij #define V3_PCI_CFG_M_RETRY_EN (1 << 10) 110*2458716aSLinus Walleij #define V3_PCI_CFG_M_AD_LOW1 (1 << 9) 111*2458716aSLinus Walleij #define V3_PCI_CFG_M_AD_LOW0 (1 << 8) 112*2458716aSLinus Walleij 113*2458716aSLinus Walleij /* PCI_BASE register bits (PCI -> Local Bus) 114*2458716aSLinus Walleij */ 115*2458716aSLinus Walleij #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 116*2458716aSLinus Walleij #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 117*2458716aSLinus Walleij #define V3_PCI_BASE_M_PREFETCH (1 << 3) 118*2458716aSLinus Walleij #define V3_PCI_BASE_M_TYPE (3 << 1) 119*2458716aSLinus Walleij #define V3_PCI_BASE_M_IO (1 << 0) 120*2458716aSLinus Walleij 121*2458716aSLinus Walleij /* PCI MAP register bits (PCI -> Local bus) 122*2458716aSLinus Walleij */ 123*2458716aSLinus Walleij #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 124*2458716aSLinus Walleij #define V3_PCI_MAP_M_RD_POST_INH (1 << 15) 125*2458716aSLinus Walleij #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) 126*2458716aSLinus Walleij #define V3_PCI_MAP_M_SWAP (3 << 8) 127*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 128*2458716aSLinus Walleij #define V3_PCI_MAP_M_REG_EN (1 << 1) 129*2458716aSLinus Walleij #define V3_PCI_MAP_M_ENABLE (1 << 0) 130*2458716aSLinus Walleij 131*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_1MB (0 << 4) 132*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_2MB (1 << 4) 133*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_4MB (2 << 4) 134*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_8MB (3 << 4) 135*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_16MB (4 << 4) 136*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_32MB (5 << 4) 137*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_64MB (6 << 4) 138*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_128MB (7 << 4) 139*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_256MB (8 << 4) 140*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_512MB (9 << 4) 141*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_1GB (10 << 4) 142*2458716aSLinus Walleij #define V3_PCI_MAP_M_ADR_SIZE_2GB (11 << 4) 143*2458716aSLinus Walleij 144*2458716aSLinus Walleij /* 145*2458716aSLinus Walleij * LB_BASE0,1 register bits (Local bus -> PCI) 146*2458716aSLinus Walleij */ 147*2458716aSLinus Walleij #define V3_LB_BASE_ADR_BASE 0xfff00000 148*2458716aSLinus Walleij #define V3_LB_BASE_SWAP (3 << 8) 149*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE (15 << 4) 150*2458716aSLinus Walleij #define V3_LB_BASE_PREFETCH (1 << 3) 151*2458716aSLinus Walleij #define V3_LB_BASE_ENABLE (1 << 0) 152*2458716aSLinus Walleij 153*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) 154*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) 155*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) 156*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) 157*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) 158*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) 159*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) 160*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) 161*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) 162*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) 163*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) 164*2458716aSLinus Walleij #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) 165*2458716aSLinus Walleij 166*2458716aSLinus Walleij #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) 167*2458716aSLinus Walleij 168*2458716aSLinus Walleij /* 169*2458716aSLinus Walleij * LB_MAP0,1 register bits (Local bus -> PCI) 170*2458716aSLinus Walleij */ 171*2458716aSLinus Walleij #define V3_LB_MAP_MAP_ADR 0xfff0 172*2458716aSLinus Walleij #define V3_LB_MAP_TYPE (7 << 1) 173*2458716aSLinus Walleij #define V3_LB_MAP_AD_LOW_EN (1 << 0) 174*2458716aSLinus Walleij 175*2458716aSLinus Walleij #define V3_LB_MAP_TYPE_IACK (0 << 1) 176*2458716aSLinus Walleij #define V3_LB_MAP_TYPE_IO (1 << 1) 177*2458716aSLinus Walleij #define V3_LB_MAP_TYPE_MEM (3 << 1) 178*2458716aSLinus Walleij #define V3_LB_MAP_TYPE_CONFIG (5 << 1) 179*2458716aSLinus Walleij #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) 180*2458716aSLinus Walleij 181*2458716aSLinus Walleij /* PCI MAP register bits (PCI -> Local bus) */ 182*2458716aSLinus Walleij #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) 183*2458716aSLinus Walleij 184*2458716aSLinus Walleij /* 185*2458716aSLinus Walleij * LB_BASE2 register bits (Local bus -> PCI IO) 186*2458716aSLinus Walleij */ 187*2458716aSLinus Walleij #define V3_LB_BASE2_ADR_BASE 0xff00 188*2458716aSLinus Walleij #define V3_LB_BASE2_SWAP (3 << 6) 189*2458716aSLinus Walleij #define V3_LB_BASE2_ENABLE (1 << 0) 190*2458716aSLinus Walleij 191*2458716aSLinus Walleij #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) 192*2458716aSLinus Walleij 193*2458716aSLinus Walleij /* 194*2458716aSLinus Walleij * LB_MAP2 register bits (Local bus -> PCI IO) 195*2458716aSLinus Walleij */ 196*2458716aSLinus Walleij #define V3_LB_MAP2_MAP_ADR 0xff00 197*2458716aSLinus Walleij 198*2458716aSLinus Walleij #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) 199*2458716aSLinus Walleij 200*2458716aSLinus Walleij #endif 201