1 /* 2 * (C) Copyright 2002 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 8 * 9 * (C) Copyright 2003 10 * Texas Instruments, <www.ti.com> 11 * Kshitij Gupta <Kshitij@ti.com> 12 * 13 * (C) Copyright 2004 14 * ARM Ltd. 15 * Philippe Robin, <philippe.robin@arm.com> 16 * 17 * (C) Copyright 2011 18 * Linaro 19 * Linus Walleij <linus.walleij@linaro.org> 20 * 21 * See file CREDITS for list of people who contributed to this 22 * project. 23 * 24 * This program is free software; you can redistribute it and/or 25 * modify it under the terms of the GNU General Public License as 26 * published by the Free Software Foundation; either version 2 of 27 * the License, or (at your option) any later version. 28 * 29 * This program is distributed in the hope that it will be useful, 30 * but WITHOUT ANY WARRANTY; without even the implied warranty of 31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 * GNU General Public License for more details. 33 * 34 * You should have received a copy of the GNU General Public License 35 * along with this program; if not, write to the Free Software 36 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 37 * MA 02111-1307 USA 38 */ 39 #include <common.h> 40 #include <pci.h> 41 #include <asm/io.h> 42 #include "integrator-sc.h" 43 #include "pci_v3.h" 44 45 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 46 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 47 48 /* 49 * These are in the physical addresses on the CPU side, i.e. 50 * where we read and write stuff - you don't want to try to 51 * move these around 52 */ 53 #define PHYS_PCI_MEM_BASE 0x40000000 54 #define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ 55 #define PHYS_PCI_CONFIG_BASE 0x61000000 56 #define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ 57 #define SZ_256M 0x10000000 58 59 /* 60 * These are in the PCI BUS address space 61 * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor 62 * we follow the example of the kernel, because that is the address 63 * range that devices actually use - what would they be doing at 64 * 0x40000000? 65 */ 66 #define PCI_BUS_NONMEM_START 0x00000000 67 #define PCI_BUS_NONMEM_SIZE SZ_256M 68 69 #define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) 70 #define PCI_BUS_PREMEM_SIZE SZ_256M 71 72 #if PCI_BUS_NONMEM_START & 0x000fffff 73 #error PCI_BUS_NONMEM_START must be megabyte aligned 74 #endif 75 #if PCI_BUS_PREMEM_START & 0x000fffff 76 #error PCI_BUS_PREMEM_START must be megabyte aligned 77 #endif 78 79 /* 80 * Initialize PCI Devices, report devices found. 81 */ 82 83 #ifndef CONFIG_PCI_PNP 84 #define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ 85 #define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ 86 static struct pci_config_table pci_integrator_config_table[] = { 87 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, 88 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, 89 PCI_ENET0_MEMADDR, 90 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, 91 { } 92 }; 93 #endif /* CONFIG_PCI_PNP */ 94 95 /* V3 access routines */ 96 #define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) 97 #define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) 98 99 #define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) 100 #define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) 101 102 #define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) 103 #define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) 104 105 static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) 106 { 107 unsigned int address, mapaddress; 108 unsigned int busnr = PCI_BUS(bdf); 109 unsigned int devfn = PCI_FUNC(bdf); 110 111 /* 112 * Trap out illegal values 113 */ 114 if (offset > 255) 115 BUG(); 116 if (busnr > 255) 117 BUG(); 118 if (devfn > 255) 119 BUG(); 120 121 if (busnr == 0) { 122 /* 123 * Linux calls the thing U-Boot calls "DEV" "SLOT" 124 * instead, but it's the same 5 bits 125 */ 126 int slot = PCI_DEV(bdf); 127 128 /* 129 * local bus segment so need a type 0 config cycle 130 * 131 * build the PCI configuration "address" with one-hot in 132 * A31-A11 133 * 134 * mapaddress: 135 * 3:1 = config cycle (101) 136 * 0 = PCI A1 & A0 are 0 (0) 137 */ 138 address = PCI_FUNC(bdf) << 8; 139 mapaddress = V3_LB_MAP_TYPE_CONFIG; 140 141 if (slot > 12) 142 /* 143 * high order bits are handled by the MAP register 144 */ 145 mapaddress |= 1 << (slot - 5); 146 else 147 /* 148 * low order bits handled directly in the address 149 */ 150 address |= 1 << (slot + 11); 151 } else { 152 /* 153 * not the local bus segment so need a type 1 config cycle 154 * 155 * address: 156 * 23:16 = bus number 157 * 15:11 = slot number (7:3 of devfn) 158 * 10:8 = func number (2:0 of devfn) 159 * 160 * mapaddress: 161 * 3:1 = config cycle (101) 162 * 0 = PCI A1 & A0 from host bus (1) 163 */ 164 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; 165 address = (busnr << 16) | (devfn << 8); 166 } 167 168 /* 169 * Set up base0 to see all 512Mbytes of memory space (not 170 * prefetchable), this frees up base1 for re-use by 171 * configuration memory 172 */ 173 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 174 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); 175 176 /* 177 * Set up base1/map1 to point into configuration space. 178 */ 179 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | 180 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); 181 v3_writew(V3_LB_MAP1, mapaddress); 182 183 return PHYS_PCI_CONFIG_BASE + address + offset; 184 } 185 186 static void v3_close_config_window(void) 187 { 188 /* 189 * Reassign base1 for use by prefetchable PCI memory 190 */ 191 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | 192 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 193 V3_LB_BASE_ENABLE); 194 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 195 V3_LB_MAP_TYPE_MEM_MULTIPLE); 196 197 /* 198 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) 199 */ 200 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 201 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); 202 } 203 204 static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, 205 int offset, unsigned char *val) 206 { 207 unsigned long addr; 208 209 addr = v3_open_config_window(bdf, offset); 210 *val = __raw_readb(addr); 211 v3_close_config_window(); 212 return 0; 213 } 214 215 static int pci_integrator_read__word(struct pci_controller *hose, 216 pci_dev_t bdf, int offset, 217 unsigned short *val) 218 { 219 unsigned long addr; 220 221 addr = v3_open_config_window(bdf, offset); 222 *val = __raw_readw(addr); 223 v3_close_config_window(); 224 return 0; 225 } 226 227 static int pci_integrator_read_dword(struct pci_controller *hose, 228 pci_dev_t bdf, int offset, 229 unsigned int *val) 230 { 231 unsigned long addr; 232 233 addr = v3_open_config_window(bdf, offset); 234 *val = __raw_readl(addr); 235 v3_close_config_window(); 236 return 0; 237 } 238 239 static int pci_integrator_write_byte(struct pci_controller *hose, 240 pci_dev_t bdf, int offset, 241 unsigned char val) 242 { 243 unsigned long addr; 244 245 addr = v3_open_config_window(bdf, offset); 246 __raw_writeb((u8)val, addr); 247 __raw_readb(addr); 248 v3_close_config_window(); 249 return 0; 250 } 251 252 static int pci_integrator_write_word(struct pci_controller *hose, 253 pci_dev_t bdf, int offset, 254 unsigned short val) 255 { 256 unsigned long addr; 257 258 addr = v3_open_config_window(bdf, offset); 259 __raw_writew((u8)val, addr); 260 __raw_readw(addr); 261 v3_close_config_window(); 262 return 0; 263 } 264 265 static int pci_integrator_write_dword(struct pci_controller *hose, 266 pci_dev_t bdf, int offset, 267 unsigned int val) 268 { 269 unsigned long addr; 270 271 addr = v3_open_config_window(bdf, offset); 272 __raw_writel((u8)val, addr); 273 __raw_readl(addr); 274 v3_close_config_window(); 275 return 0; 276 } 277 278 struct pci_controller integrator_hose = { 279 #ifndef CONFIG_PCI_PNP 280 config_table: pci_integrator_config_table, 281 #endif 282 }; 283 284 void pci_init_board(void) 285 { 286 struct pci_controller *hose = &integrator_hose; 287 u16 val; 288 289 /* setting this register will take the V3 out of reset */ 290 __raw_writel(SC_PCI_PCIEN, SC_PCI); 291 292 /* Wait for 230 ms (from spec) before accessing any V3 registers */ 293 mdelay(230); 294 295 /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ 296 v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); 297 298 /* Wait for the mailbox to settle */ 299 do { 300 v3_writeb(V3_MAIL_DATA, 0xAA); 301 v3_writeb(V3_MAIL_DATA + 4, 0x55); 302 } while (v3_readb(V3_MAIL_DATA) != 0xAA || 303 v3_readb(V3_MAIL_DATA + 4) != 0x55); 304 305 /* Make sure that V3 register access is not locked, if it is, unlock it */ 306 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) 307 v3_writew(V3_SYSTEM, 0xA05F); 308 309 /* 310 * Ensure that the slave accesses from PCI are disabled while we 311 * setup memory windows 312 */ 313 val = v3_readw(V3_PCI_CMD); 314 val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); 315 v3_writew(V3_PCI_CMD, val); 316 317 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ 318 val = v3_readw(V3_SYSTEM); 319 val &= ~V3_SYSTEM_M_RST_OUT; 320 v3_writew(V3_SYSTEM, val); 321 322 /* Make all accesses from PCI space retry until we're ready for them */ 323 val = v3_readw(V3_PCI_CFG); 324 val |= V3_PCI_CFG_M_RETRY_EN; 325 v3_writew(V3_PCI_CFG, val); 326 327 /* 328 * Set up any V3 PCI Configuration Registers that we absolutely have to. 329 * LB_CFG controls Local Bus protocol. 330 * Enable LocalBus byte strobes for READ accesses too. 331 * set bit 7 BE_IMODE and bit 6 BE_OMODE 332 */ 333 val = v3_readw(V3_LB_CFG); 334 val |= 0x0C0; 335 v3_writew(V3_LB_CFG, val); 336 337 /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ 338 val = v3_readw(V3_PCI_CMD); 339 val |= V3_COMMAND_M_MASTER_EN; 340 v3_writew(V3_PCI_CMD, val); 341 342 /* 343 * PCI_MAP0 controls where the PCI to CPU memory window is on 344 * Local Bus 345 */ 346 v3_writel(V3_PCI_MAP0, 347 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | 348 V3_PCI_MAP_M_REG_EN | 349 V3_PCI_MAP_M_ENABLE)); 350 351 /* PCI_BASE0 is the PCI address of the start of the window */ 352 v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); 353 354 /* PCI_MAP1 is LOCAL address of the start of the window */ 355 v3_writel(V3_PCI_MAP1, 356 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | 357 V3_PCI_MAP_M_REG_EN | 358 V3_PCI_MAP_M_ENABLE)); 359 360 /* PCI_BASE1 is the PCI address of the start of the window */ 361 v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); 362 363 /* 364 * Set up memory the windows from local bus memory into PCI 365 * configuration, I/O and Memory regions. 366 * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. 367 */ 368 v3_writew(V3_LB_BASE2, 369 v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); 370 v3_writew(V3_LB_MAP2, 0); 371 372 /* PCI Configuration, use LB_BASE1/LB_MAP1. */ 373 374 /* 375 * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 376 * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 377 */ 378 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 379 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); 380 v3_writew(V3_LB_MAP0, 381 v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); 382 383 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ 384 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | 385 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 386 V3_LB_BASE_ENABLE); 387 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 388 V3_LB_MAP_TYPE_MEM_MULTIPLE); 389 390 /* Dump PCI to local address space mappings */ 391 debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); 392 debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); 393 debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); 394 debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); 395 debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); 396 debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); 397 debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); 398 399 /* 400 * Allow accesses to PCI Configuration space and set up A1, A0 for 401 * type 1 config cycles 402 */ 403 val = v3_readw(V3_PCI_CFG); 404 val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); 405 val |= V3_PCI_CFG_M_AD_LOW0; 406 v3_writew(V3_PCI_CFG, val); 407 408 /* now we can allow incoming PCI MEMORY accesses */ 409 val = v3_readw(V3_PCI_CMD); 410 val |= V3_COMMAND_M_MEM_EN; 411 v3_writew(V3_PCI_CMD, val); 412 413 /* 414 * Set RST_OUT to take the PCI bus is out of reset, PCI devices can 415 * now initialise. 416 */ 417 val = v3_readw(V3_SYSTEM); 418 val |= V3_SYSTEM_M_RST_OUT; 419 v3_writew(V3_SYSTEM, val); 420 421 /* Lock the V3 system register so that no one else can play with it */ 422 val = v3_readw(V3_SYSTEM); 423 val |= V3_SYSTEM_M_LOCK; 424 v3_writew(V3_SYSTEM, val); 425 426 /* 427 * Configure and register the PCI hose 428 */ 429 hose->first_busno = 0; 430 hose->last_busno = 0xff; 431 432 /* System memory space, window 0 256 MB non-prefetchable */ 433 pci_set_region(hose->regions + 0, 434 PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, 435 SZ_256M, 436 PCI_REGION_MEM); 437 438 /* System memory space, window 1 256 MB prefetchable */ 439 pci_set_region(hose->regions + 1, 440 PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, 441 SZ_256M, 442 PCI_REGION_MEM | 443 PCI_REGION_PREFETCH); 444 445 /* PCI I/O space */ 446 pci_set_region(hose->regions + 2, 447 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, 448 PCI_REGION_IO); 449 450 /* PCI Memory - config space */ 451 pci_set_region(hose->regions + 3, 452 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, 453 PCI_REGION_MEM); 454 /* PCI V3 regs */ 455 pci_set_region(hose->regions + 4, 456 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, 457 PCI_REGION_MEM); 458 459 hose->region_count = 5; 460 461 pci_set_ops(hose, 462 pci_integrator_read_byte, 463 pci_integrator_read__word, 464 pci_integrator_read_dword, 465 pci_integrator_write_byte, 466 pci_integrator_write_word, 467 pci_integrator_write_dword); 468 469 pci_register_hose(hose); 470 471 pciauto_config_init(hose); 472 pciauto_config_device(hose, 0); 473 474 hose->last_busno = pci_hose_scan(hose); 475 } 476