1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2002 4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 5 * Marius Groeger <mgroeger@sysgo.de> 6 * 7 * (C) Copyright 2002 8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 9 * 10 * (C) Copyright 2003 11 * Texas Instruments, <www.ti.com> 12 * Kshitij Gupta <Kshitij@ti.com> 13 * 14 * (C) Copyright 2004 15 * ARM Ltd. 16 * Philippe Robin, <philippe.robin@arm.com> 17 * 18 * (C) Copyright 2011 19 * Linaro 20 * Linus Walleij <linus.walleij@linaro.org> 21 */ 22 #include <common.h> 23 #include <pci.h> 24 #include <asm/io.h> 25 #include "integrator-sc.h" 26 #include "pci_v3.h" 27 28 #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 29 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 30 31 /* 32 * These are in the physical addresses on the CPU side, i.e. 33 * where we read and write stuff - you don't want to try to 34 * move these around 35 */ 36 #define PHYS_PCI_MEM_BASE 0x40000000 37 #define PHYS_PCI_IO_BASE 0x60000000 /* PCI I/O space base */ 38 #define PHYS_PCI_CONFIG_BASE 0x61000000 39 #define PHYS_PCI_V3_BASE 0x62000000 /* V360EPC registers */ 40 #define SZ_256M 0x10000000 41 42 /* 43 * These are in the PCI BUS address space 44 * Set to 0x00000000 in the Linux kernel, 0x40000000 in Boot monitor 45 * we follow the example of the kernel, because that is the address 46 * range that devices actually use - what would they be doing at 47 * 0x40000000? 48 */ 49 #define PCI_BUS_NONMEM_START 0x00000000 50 #define PCI_BUS_NONMEM_SIZE SZ_256M 51 52 #define PCI_BUS_PREMEM_START (PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE) 53 #define PCI_BUS_PREMEM_SIZE SZ_256M 54 55 #if PCI_BUS_NONMEM_START & 0x000fffff 56 #error PCI_BUS_NONMEM_START must be megabyte aligned 57 #endif 58 #if PCI_BUS_PREMEM_START & 0x000fffff 59 #error PCI_BUS_PREMEM_START must be megabyte aligned 60 #endif 61 62 /* 63 * Initialize PCI Devices, report devices found. 64 */ 65 66 #ifndef CONFIG_PCI_PNP 67 #define PCI_ENET0_IOADDR 0x60000000 /* First card in PCI I/O space */ 68 #define PCI_ENET0_MEMADDR 0x40000000 /* First card in PCI memory space */ 69 static struct pci_config_table pci_integrator_config_table[] = { 70 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, 71 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, 72 PCI_ENET0_MEMADDR, 73 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, 74 { } 75 }; 76 #endif /* CONFIG_PCI_PNP */ 77 78 /* V3 access routines */ 79 #define v3_writeb(o, v) __raw_writeb(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) 80 #define v3_readb(o) (__raw_readb(PHYS_PCI_V3_BASE + (unsigned int)(o))) 81 82 #define v3_writew(o, v) __raw_writew(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) 83 #define v3_readw(o) (__raw_readw(PHYS_PCI_V3_BASE + (unsigned int)(o))) 84 85 #define v3_writel(o, v) __raw_writel(v, PHYS_PCI_V3_BASE + (unsigned int)(o)) 86 #define v3_readl(o) (__raw_readl(PHYS_PCI_V3_BASE + (unsigned int)(o))) 87 88 static unsigned long v3_open_config_window(pci_dev_t bdf, int offset) 89 { 90 unsigned int address, mapaddress; 91 unsigned int busnr = PCI_BUS(bdf); 92 unsigned int devfn = PCI_FUNC(bdf); 93 94 /* 95 * Trap out illegal values 96 */ 97 if (offset > 255) 98 BUG(); 99 if (busnr > 255) 100 BUG(); 101 if (devfn > 255) 102 BUG(); 103 104 if (busnr == 0) { 105 /* 106 * Linux calls the thing U-Boot calls "DEV" "SLOT" 107 * instead, but it's the same 5 bits 108 */ 109 int slot = PCI_DEV(bdf); 110 111 /* 112 * local bus segment so need a type 0 config cycle 113 * 114 * build the PCI configuration "address" with one-hot in 115 * A31-A11 116 * 117 * mapaddress: 118 * 3:1 = config cycle (101) 119 * 0 = PCI A1 & A0 are 0 (0) 120 */ 121 address = PCI_FUNC(bdf) << 8; 122 mapaddress = V3_LB_MAP_TYPE_CONFIG; 123 124 if (slot > 12) 125 /* 126 * high order bits are handled by the MAP register 127 */ 128 mapaddress |= 1 << (slot - 5); 129 else 130 /* 131 * low order bits handled directly in the address 132 */ 133 address |= 1 << (slot + 11); 134 } else { 135 /* 136 * not the local bus segment so need a type 1 config cycle 137 * 138 * address: 139 * 23:16 = bus number 140 * 15:11 = slot number (7:3 of devfn) 141 * 10:8 = func number (2:0 of devfn) 142 * 143 * mapaddress: 144 * 3:1 = config cycle (101) 145 * 0 = PCI A1 & A0 from host bus (1) 146 */ 147 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; 148 address = (busnr << 16) | (devfn << 8); 149 } 150 151 /* 152 * Set up base0 to see all 512Mbytes of memory space (not 153 * prefetchable), this frees up base1 for re-use by 154 * configuration memory 155 */ 156 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 157 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); 158 159 /* 160 * Set up base1/map1 to point into configuration space. 161 */ 162 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | 163 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); 164 v3_writew(V3_LB_MAP1, mapaddress); 165 166 return PHYS_PCI_CONFIG_BASE + address + offset; 167 } 168 169 static void v3_close_config_window(void) 170 { 171 /* 172 * Reassign base1 for use by prefetchable PCI memory 173 */ 174 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | 175 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 176 V3_LB_BASE_ENABLE); 177 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 178 V3_LB_MAP_TYPE_MEM_MULTIPLE); 179 180 /* 181 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) 182 */ 183 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 184 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); 185 } 186 187 static int pci_integrator_read_byte(struct pci_controller *hose, pci_dev_t bdf, 188 int offset, unsigned char *val) 189 { 190 unsigned long addr; 191 192 addr = v3_open_config_window(bdf, offset); 193 *val = __raw_readb(addr); 194 v3_close_config_window(); 195 return 0; 196 } 197 198 static int pci_integrator_read__word(struct pci_controller *hose, 199 pci_dev_t bdf, int offset, 200 unsigned short *val) 201 { 202 unsigned long addr; 203 204 addr = v3_open_config_window(bdf, offset); 205 *val = __raw_readw(addr); 206 v3_close_config_window(); 207 return 0; 208 } 209 210 static int pci_integrator_read_dword(struct pci_controller *hose, 211 pci_dev_t bdf, int offset, 212 unsigned int *val) 213 { 214 unsigned long addr; 215 216 addr = v3_open_config_window(bdf, offset); 217 *val = __raw_readl(addr); 218 v3_close_config_window(); 219 return 0; 220 } 221 222 static int pci_integrator_write_byte(struct pci_controller *hose, 223 pci_dev_t bdf, int offset, 224 unsigned char val) 225 { 226 unsigned long addr; 227 228 addr = v3_open_config_window(bdf, offset); 229 __raw_writeb((u8)val, addr); 230 __raw_readb(addr); 231 v3_close_config_window(); 232 return 0; 233 } 234 235 static int pci_integrator_write_word(struct pci_controller *hose, 236 pci_dev_t bdf, int offset, 237 unsigned short val) 238 { 239 unsigned long addr; 240 241 addr = v3_open_config_window(bdf, offset); 242 __raw_writew((u8)val, addr); 243 __raw_readw(addr); 244 v3_close_config_window(); 245 return 0; 246 } 247 248 static int pci_integrator_write_dword(struct pci_controller *hose, 249 pci_dev_t bdf, int offset, 250 unsigned int val) 251 { 252 unsigned long addr; 253 254 addr = v3_open_config_window(bdf, offset); 255 __raw_writel((u8)val, addr); 256 __raw_readl(addr); 257 v3_close_config_window(); 258 return 0; 259 } 260 261 struct pci_controller integrator_hose = { 262 #ifndef CONFIG_PCI_PNP 263 config_table: pci_integrator_config_table, 264 #endif 265 }; 266 267 void pci_init_board(void) 268 { 269 struct pci_controller *hose = &integrator_hose; 270 u16 val; 271 272 /* setting this register will take the V3 out of reset */ 273 __raw_writel(SC_PCI_PCIEN, SC_PCI); 274 275 /* Wait for 230 ms (from spec) before accessing any V3 registers */ 276 mdelay(230); 277 278 /* Now write the Base I/O Address Word to PHYS_PCI_V3_BASE + 0x6E */ 279 v3_writew(V3_LB_IO_BASE, (PHYS_PCI_V3_BASE >> 16)); 280 281 /* Wait for the mailbox to settle */ 282 do { 283 v3_writeb(V3_MAIL_DATA, 0xAA); 284 v3_writeb(V3_MAIL_DATA + 4, 0x55); 285 } while (v3_readb(V3_MAIL_DATA) != 0xAA || 286 v3_readb(V3_MAIL_DATA + 4) != 0x55); 287 288 /* Make sure that V3 register access is not locked, if it is, unlock it */ 289 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) 290 v3_writew(V3_SYSTEM, 0xA05F); 291 292 /* 293 * Ensure that the slave accesses from PCI are disabled while we 294 * setup memory windows 295 */ 296 val = v3_readw(V3_PCI_CMD); 297 val &= ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); 298 v3_writew(V3_PCI_CMD, val); 299 300 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ 301 val = v3_readw(V3_SYSTEM); 302 val &= ~V3_SYSTEM_M_RST_OUT; 303 v3_writew(V3_SYSTEM, val); 304 305 /* Make all accesses from PCI space retry until we're ready for them */ 306 val = v3_readw(V3_PCI_CFG); 307 val |= V3_PCI_CFG_M_RETRY_EN; 308 v3_writew(V3_PCI_CFG, val); 309 310 /* 311 * Set up any V3 PCI Configuration Registers that we absolutely have to. 312 * LB_CFG controls Local Bus protocol. 313 * Enable LocalBus byte strobes for READ accesses too. 314 * set bit 7 BE_IMODE and bit 6 BE_OMODE 315 */ 316 val = v3_readw(V3_LB_CFG); 317 val |= 0x0C0; 318 v3_writew(V3_LB_CFG, val); 319 320 /* PCI_CMD controls overall PCI operation. Enable PCI bus master. */ 321 val = v3_readw(V3_PCI_CMD); 322 val |= V3_COMMAND_M_MASTER_EN; 323 v3_writew(V3_PCI_CMD, val); 324 325 /* 326 * PCI_MAP0 controls where the PCI to CPU memory window is on 327 * Local Bus 328 */ 329 v3_writel(V3_PCI_MAP0, 330 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512MB | 331 V3_PCI_MAP_M_REG_EN | 332 V3_PCI_MAP_M_ENABLE)); 333 334 /* PCI_BASE0 is the PCI address of the start of the window */ 335 v3_writel(V3_PCI_BASE0, INTEGRATOR_BOOT_ROM_BASE); 336 337 /* PCI_MAP1 is LOCAL address of the start of the window */ 338 v3_writel(V3_PCI_MAP1, 339 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1GB | 340 V3_PCI_MAP_M_REG_EN | 341 V3_PCI_MAP_M_ENABLE)); 342 343 /* PCI_BASE1 is the PCI address of the start of the window */ 344 v3_writel(V3_PCI_BASE1, INTEGRATOR_HDR0_SDRAM_BASE); 345 346 /* 347 * Set up memory the windows from local bus memory into PCI 348 * configuration, I/O and Memory regions. 349 * PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. 350 */ 351 v3_writew(V3_LB_BASE2, 352 v3_addr_to_lb_map(PHYS_PCI_IO_BASE) | V3_LB_BASE_ENABLE); 353 v3_writew(V3_LB_MAP2, 0); 354 355 /* PCI Configuration, use LB_BASE1/LB_MAP1. */ 356 357 /* 358 * PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 359 * Map first 256Mbytes as non-prefetchable via BASE0/MAP0 360 */ 361 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 362 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); 363 v3_writew(V3_LB_MAP0, 364 v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | V3_LB_MAP_TYPE_MEM); 365 366 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ 367 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | 368 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 369 V3_LB_BASE_ENABLE); 370 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 371 V3_LB_MAP_TYPE_MEM_MULTIPLE); 372 373 /* Dump PCI to local address space mappings */ 374 debug("LB_BASE0 = %08x\n", v3_readl(V3_LB_BASE0)); 375 debug("LB_MAP0 = %04x\n", v3_readw(V3_LB_MAP0)); 376 debug("LB_BASE1 = %08x\n", v3_readl(V3_LB_BASE1)); 377 debug("LB_MAP1 = %04x\n", v3_readw(V3_LB_MAP1)); 378 debug("LB_BASE2 = %04x\n", v3_readw(V3_LB_BASE2)); 379 debug("LB_MAP2 = %04x\n", v3_readw(V3_LB_MAP2)); 380 debug("LB_IO_BASE = %04x\n", v3_readw(V3_LB_IO_BASE)); 381 382 /* 383 * Allow accesses to PCI Configuration space and set up A1, A0 for 384 * type 1 config cycles 385 */ 386 val = v3_readw(V3_PCI_CFG); 387 val &= ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1); 388 val |= V3_PCI_CFG_M_AD_LOW0; 389 v3_writew(V3_PCI_CFG, val); 390 391 /* now we can allow incoming PCI MEMORY accesses */ 392 val = v3_readw(V3_PCI_CMD); 393 val |= V3_COMMAND_M_MEM_EN; 394 v3_writew(V3_PCI_CMD, val); 395 396 /* 397 * Set RST_OUT to take the PCI bus is out of reset, PCI devices can 398 * now initialise. 399 */ 400 val = v3_readw(V3_SYSTEM); 401 val |= V3_SYSTEM_M_RST_OUT; 402 v3_writew(V3_SYSTEM, val); 403 404 /* Lock the V3 system register so that no one else can play with it */ 405 val = v3_readw(V3_SYSTEM); 406 val |= V3_SYSTEM_M_LOCK; 407 v3_writew(V3_SYSTEM, val); 408 409 /* 410 * Configure and register the PCI hose 411 */ 412 hose->first_busno = 0; 413 hose->last_busno = 0xff; 414 415 /* System memory space, window 0 256 MB non-prefetchable */ 416 pci_set_region(hose->regions + 0, 417 PCI_BUS_NONMEM_START, PHYS_PCI_MEM_BASE, 418 SZ_256M, 419 PCI_REGION_MEM); 420 421 /* System memory space, window 1 256 MB prefetchable */ 422 pci_set_region(hose->regions + 1, 423 PCI_BUS_PREMEM_START, PHYS_PCI_MEM_BASE + SZ_256M, 424 SZ_256M, 425 PCI_REGION_MEM | 426 PCI_REGION_PREFETCH); 427 428 /* PCI I/O space */ 429 pci_set_region(hose->regions + 2, 430 0x00000000, PHYS_PCI_IO_BASE, 0x01000000, 431 PCI_REGION_IO); 432 433 /* PCI Memory - config space */ 434 pci_set_region(hose->regions + 3, 435 0x00000000, PHYS_PCI_CONFIG_BASE, 0x01000000, 436 PCI_REGION_MEM); 437 /* PCI V3 regs */ 438 pci_set_region(hose->regions + 4, 439 0x00000000, PHYS_PCI_V3_BASE, 0x01000000, 440 PCI_REGION_MEM); 441 442 hose->region_count = 5; 443 444 pci_set_ops(hose, 445 pci_integrator_read_byte, 446 pci_integrator_read__word, 447 pci_integrator_read_dword, 448 pci_integrator_write_byte, 449 pci_integrator_write_word, 450 pci_integrator_write_dword); 451 452 pci_register_hose(hose); 453 454 pciauto_config_init(hose); 455 pciauto_config_device(hose, 0); 456 457 hose->last_busno = pci_hose_scan(hose); 458 } 459