1 /* 2 * (C) Copyright 2002 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 8 * 9 * (C) Copyright 2003 10 * Texas Instruments, <www.ti.com> 11 * Kshitij Gupta <Kshitij@ti.com> 12 * 13 * (C) Copyright 2004 14 * ARM Ltd. 15 * Philippe Robin, <philippe.robin@arm.com> 16 * 17 * See file CREDITS for list of people who contributed to this 18 * project. 19 * 20 * This program is free software; you can redistribute it and/or 21 * modify it under the terms of the GNU General Public License as 22 * published by the Free Software Foundation; either version 2 of 23 * the License, or (at your option) any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; if not, write to the Free Software 32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 33 * MA 02111-1307 USA 34 */ 35 36 #include <common.h> 37 #include <pci.h> 38 39 /* 40 * Initialize PCI Devices, report devices found. 41 */ 42 43 #ifndef CONFIG_PCI_PNP 44 static struct pci_config_table pci_integrator_config_table[] = { 45 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID, 46 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, 47 PCI_ENET0_MEMADDR, 48 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }}, 49 { } 50 }; 51 #endif /* CONFIG_PCI_PNP */ 52 53 /* V3 access routines */ 54 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v)) 55 #define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o))) 56 57 #define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v)) 58 #define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o))) 59 60 /* Compute address necessary to access PCI config space for the given */ 61 /* bus and device. */ 62 #define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \ 63 unsigned int __address, __devicebit; \ 64 unsigned short __mapaddress; \ 65 unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \ 66 \ 67 if (__bus == 0) { \ 68 /* local bus segment so need a type 0 config cycle */ \ 69 /* build the PCI configuration "address" with one-hot in A31-A11 */ \ 70 __address = PCI_CONFIG_BASE; \ 71 __address |= ((__devfn & 0x07) << 8); \ 72 __address |= __offset & 0xFF; \ 73 __mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \ 74 __devicebit = (1 << (__dev + 11)); \ 75 \ 76 if ((__devicebit & 0xFF000000) != 0) { \ 77 /* high order bits are handled by the MAP register */ \ 78 __mapaddress |= (__devicebit >> 16); \ 79 } else { \ 80 /* low order bits handled directly in the address */ \ 81 __address |= __devicebit; \ 82 } \ 83 } else { /* bus !=0 */ \ 84 /* not the local bus segment so need a type 1 config cycle */ \ 85 /* A31-A24 are don't care (so clear to 0) */ \ 86 __mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \ 87 __address = PCI_CONFIG_BASE; \ 88 __address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \ 89 __address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \ 90 __address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number */ \ 91 __address |= __offset & 0xFF; /* bits 7..0 = register number */ \ 92 } \ 93 _V3Write16 (V3_LB_MAP1, __mapaddress); \ 94 __address; \ 95 }) 96 97 /* _V3OpenConfigWindow - open V3 configuration window */ 98 #define _V3OpenConfigWindow() { \ 99 /* Set up base0 to see all 512Mbytes of memory space (not */ \ 100 /* prefetchable), this frees up base1 for re-use by configuration*/ \ 101 /* memory */ \ 102 \ 103 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ 104 0x90 | V3_LB_BASE_M_ENABLE)); \ 105 /* Set up base1 to point into configuration space, note that MAP1 */ \ 106 /* register is set up by pciMakeConfigAddress(). */ \ 107 \ 108 _V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \ 109 0x40 | V3_LB_BASE_M_ENABLE)); \ 110 } 111 112 /* _V3CloseConfigWindow - close V3 configuration window */ 113 #define _V3CloseConfigWindow() { \ 114 /* Reassign base1 for use by prefetchable PCI memory */ \ 115 _V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \ 116 | 0x84 | V3_LB_BASE_M_ENABLE)); \ 117 _V3Write16 (V3_LB_MAP1, \ 118 (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) >> 16) | 0x0006); \ 119 \ 120 /* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \ 121 \ 122 _V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \ 123 0x80 | V3_LB_BASE_M_ENABLE)); \ 124 } 125 126 static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev, 127 int offset, unsigned char *val) 128 { 129 _V3OpenConfigWindow (); 130 *val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), 131 PCI_FUNC (dev), 132 offset); 133 _V3CloseConfigWindow (); 134 135 return 0; 136 } 137 138 static int pci_integrator_read__word (struct pci_controller *hose, 139 pci_dev_t dev, int offset, 140 unsigned short *val) 141 { 142 _V3OpenConfigWindow (); 143 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), 144 PCI_FUNC (dev), 145 offset); 146 _V3CloseConfigWindow (); 147 148 return 0; 149 } 150 151 static int pci_integrator_read_dword (struct pci_controller *hose, 152 pci_dev_t dev, int offset, 153 unsigned int *val) 154 { 155 _V3OpenConfigWindow (); 156 *val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), 157 PCI_FUNC (dev), 158 offset); 159 *val |= (*(volatile unsigned int *) 160 PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev), 161 (offset + 2))) << 16; 162 _V3CloseConfigWindow (); 163 164 return 0; 165 } 166 167 static int pci_integrator_write_byte (struct pci_controller *hose, 168 pci_dev_t dev, int offset, 169 unsigned char val) 170 { 171 _V3OpenConfigWindow (); 172 *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), 173 PCI_FUNC (dev), 174 offset) = val; 175 _V3CloseConfigWindow (); 176 177 return 0; 178 } 179 180 static int pci_integrator_write_word (struct pci_controller *hose, 181 pci_dev_t dev, int offset, 182 unsigned short val) 183 { 184 _V3OpenConfigWindow (); 185 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), 186 PCI_FUNC (dev), 187 offset) = val; 188 _V3CloseConfigWindow (); 189 190 return 0; 191 } 192 193 static int pci_integrator_write_dword (struct pci_controller *hose, 194 pci_dev_t dev, int offset, 195 unsigned int val) 196 { 197 _V3OpenConfigWindow (); 198 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), 199 PCI_FUNC (dev), 200 offset) = (val & 0xFFFF); 201 *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), 202 PCI_FUNC (dev), 203 (offset + 2)) = ((val >> 16) & 0xFFFF); 204 _V3CloseConfigWindow (); 205 206 return 0; 207 } 208 /****************************** 209 * PCI initialisation 210 ******************************/ 211 212 struct pci_controller integrator_hose = { 213 #ifndef CONFIG_PCI_PNP 214 config_table: pci_integrator_config_table, 215 #endif 216 }; 217 218 void pci_init_board (void) 219 { 220 volatile int i, j; 221 struct pci_controller *hose = &integrator_hose; 222 223 /* setting this register will take the V3 out of reset */ 224 225 *(volatile unsigned int *) (INTEGRATOR_SC_PCIENABLE) = 1; 226 227 /* wait a few usecs to settle the device and the PCI bus */ 228 229 for (i = 0; i < 100; i++) 230 j = i + 1; 231 232 /* Now write the Base I/O Address Word to V3_BASE + 0x6C */ 233 234 *(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) = 235 (unsigned short) (V3_BASE >> 16); 236 237 do { 238 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA; 239 *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) = 240 0x55; 241 } while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA 242 || *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 243 4) != 0x55); 244 245 /* Make sure that V3 register access is not locked, if it is, unlock it */ 246 247 if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) & 248 V3_SYSTEM_M_LOCK) 249 == V3_SYSTEM_M_LOCK) 250 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F; 251 252 /* Ensure that the slave accesses from PCI are disabled while we */ 253 /* setup windows */ 254 255 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) &= 256 ~(V3_COMMAND_M_MEM_EN | V3_COMMAND_M_IO_EN); 257 258 /* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ 259 260 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &= 261 ~V3_SYSTEM_M_RST_OUT; 262 263 /* Make all accesses from PCI space retry until we're ready for them */ 264 265 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |= 266 V3_PCI_CFG_M_RETRY_EN; 267 268 /* Set up any V3 PCI Configuration Registers that we absolutely have to */ 269 /* LB_CFG controls Local Bus protocol. */ 270 /* Enable LocalBus byte strobes for READ accesses too. */ 271 /* set bit 7 BE_IMODE and bit 6 BE_OMODE */ 272 273 *(volatile unsigned short *) (V3_BASE + V3_LB_CFG) |= 0x0C0; 274 275 /* PCI_CMD controls overall PCI operation. */ 276 /* Enable PCI bus master. */ 277 278 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) |= 0x04; 279 280 /* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */ 281 282 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) = 283 (INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M | 284 V3_PCI_MAP_M_REG_EN | 285 V3_PCI_MAP_M_ENABLE); 286 287 /* PCI_BASE0 is the PCI address of the start of the window */ 288 289 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) = 290 INTEGRATOR_BOOT_ROM_BASE; 291 292 /* PCI_MAP1 is LOCAL address of the start of the window */ 293 294 *(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) = 295 (INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M | 296 V3_PCI_MAP_M_REG_EN | 297 V3_PCI_MAP_M_ENABLE); 298 299 /* PCI_BASE1 is the PCI address of the start of the window */ 300 301 *(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) = 302 INTEGRATOR_HDR0_SDRAM_BASE; 303 304 /* Set up the windows from local bus memory into PCI configuration, */ 305 /* I/O and Memory. */ 306 /* PCI I/O, LB_BASE2 and LB_MAP2 are used exclusively for this. */ 307 308 *(volatile unsigned short *) (V3_BASE + V3_LB_BASE2) = 309 ((CPU_PCI_IO_ADRS >> 24) << 8) | V3_LB_BASE_M_ENABLE; 310 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP2) = 0; 311 312 /* PCI Configuration, use LB_BASE1/LB_MAP1. */ 313 314 /* PCI Memory use LB_BASE0/LB_MAP0 and LB_BASE1/LB_MAP1 */ 315 /* Map first 256Mbytes as non-prefetchable via BASE0/MAP0 */ 316 /* (INTEGRATOR_PCI_BASE == PCI_MEM_BASE) */ 317 318 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE0) = 319 INTEGRATOR_PCI_BASE | (0x80 | V3_LB_BASE_M_ENABLE); 320 321 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP0) = 322 ((INTEGRATOR_PCI_BASE >> 20) << 0x4) | 0x0006; 323 324 /* Map second 256 Mbytes as prefetchable via BASE1/MAP1 */ 325 326 *(volatile unsigned int *) (V3_BASE + V3_LB_BASE1) = 327 INTEGRATOR_PCI_BASE | (0x84 | V3_LB_BASE_M_ENABLE); 328 329 *(volatile unsigned short *) (V3_BASE + V3_LB_MAP1) = 330 (((INTEGRATOR_PCI_BASE + 0x10000000) >> 20) << 4) | 0x0006; 331 332 /* Allow accesses to PCI Configuration space */ 333 /* and set up A1, A0 for type 1 config cycles */ 334 335 *(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) = 336 ((*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG)) & 337 ~(V3_PCI_CFG_M_RETRY_EN | V3_PCI_CFG_M_AD_LOW1)) | 338 V3_PCI_CFG_M_AD_LOW0; 339 340 /* now we can allow in PCI MEMORY accesses */ 341 342 *(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) = 343 (*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) | 344 V3_COMMAND_M_MEM_EN; 345 346 /* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */ 347 /* initialise and lock the V3 system register so that no one else */ 348 /* can play with it */ 349 350 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 351 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | 352 V3_SYSTEM_M_RST_OUT; 353 354 *(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 355 (*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | 356 V3_SYSTEM_M_LOCK; 357 358 /* 359 * Register the hose 360 */ 361 hose->first_busno = 0; 362 hose->last_busno = 0xff; 363 364 /* System memory space */ 365 pci_set_region (hose->regions + 0, 366 0x00000000, 0x40000000, 0x01000000, 367 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 368 369 /* PCI Memory - config space */ 370 pci_set_region (hose->regions + 1, 371 0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM); 372 373 /* PCI V3 regs */ 374 pci_set_region (hose->regions + 2, 375 0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM); 376 377 /* PCI I/O space */ 378 pci_set_region (hose->regions + 3, 379 0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO); 380 381 pci_set_ops (hose, 382 pci_integrator_read_byte, 383 pci_integrator_read__word, 384 pci_integrator_read_dword, 385 pci_integrator_write_byte, 386 pci_integrator_write_word, pci_integrator_write_dword); 387 388 hose->region_count = 4; 389 390 pci_register_hose (hose); 391 392 pciauto_config_init (hose); 393 pciauto_config_device (hose, 0); 394 395 hose->last_busno = pci_hose_scan (hose); 396 } 397