1/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2004, ARM Ltd.
5 * Philippe Robin, <philippe.robin@arm.com>
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10#include <config.h>
11
12	/* Reset using CM control register */
13.global reset_cpu
14reset_cpu:
15	mov	r0, #CM_BASE
16	ldr	r1,[r0,#OS_CTRL]
17	orr	r1,r1,#CMMASK_RESET
18	str	r1,[r0,#OS_CTRL]
19
20reset_failed:
21	b	reset_failed
22
23/* Set up the platform, once the cpu has been initialized */
24.globl lowlevel_init
25lowlevel_init:
26	/* If U-Boot has been run after the ARM boot monitor
27	 * then all the necessary actions have been done
28	 * otherwise we are running from user flash mapped to 0x00000000
29	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
30	 * Changes to the (possibly soft) reset defaults of the processor
31	 * itself should be performed in cpu/arm<>/start.S
32	 * This function affects only the core module or board settings
33	 */
34
35#ifdef CONFIG_CM_INIT
36	/* CM has an initialization register
37	 * - bits in it are wired into test-chip pins to force
38	 *   reset defaults
39	 * - may need to change its contents for U-Boot
40	 */
41
42	/* set the desired CM specific value */
43	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
44
45#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
46	orr	r2,r2,#CMMASK_INIT_102
47#else
48
49#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
50     !defined (CONFIG_CM940T)
51
52#ifdef	CONFIG_CM_MULTIPLE_SSRAM
53	/* set simple mapping			*/
54	and	r2,r2,#CMMASK_MAP_SIMPLE
55#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
56
57#ifdef	CONFIG_CM_TCRAM
58	/* disable TCRAM			*/
59	and	r2,r2,#CMMASK_TCRAM_DISABLE
60#endif /* #ifdef CONFIG_CM_TCRAM		*/
61
62#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
63     defined (CONFIG_CM1136JF_S)
64
65	and	r2,r2,#CMMASK_LE
66
67#endif /* cpu with little endian initialization */
68
69	orr	r2,r2,#CMMASK_CMxx6_COMMON
70
71#endif /* CMxx6 code */
72
73#endif /* ARM102xxE value */
74
75	/* read CM_INIT		 */
76	mov	r0, #CM_BASE
77	ldr	r1, [r0, #OS_INIT]
78	/* check against desired bit setting */
79	and	r3,r1,r2
80	cmp	r3,r2
81	beq	init_reg_OK
82
83	/* lock for change */
84	mov	r3, #CMVAL_LOCK1
85	add	r3,r3,#CMVAL_LOCK2
86	str	r3, [r0, #OS_LOCK]
87	/* set desired value */
88	orr	r1,r1,r2
89	/* write & relock CM_INIT */
90	str	r1, [r0, #OS_INIT]
91	mov	r1, #CMVAL_UNLOCK
92	str	r1, [r0, #OS_LOCK]
93
94	/* soft reset so new values used */
95	b	reset_cpu
96
97init_reg_OK:
98
99#endif /* CONFIG_CM_INIT */
100
101	mov	pc, lr
102
103#ifdef	CONFIG_CM_SPD_DETECT
104	/* Fast memory is available for the DRAM data
105	 * - ensure it has been transferred, then summarize the data
106	 *   into a CM register
107	 */
108.globl dram_query
109dram_query:
110	stmfd	r13!,{r4-r6,lr}
111	/* set up SDRAM info					*/
112	/* - based on example code from the CM User Guide */
113	mov	r0, #CM_BASE
114
115readspdbit:
116	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register	*/
117	and	r1, r1, #0x20		/* mask SPD bit (5)		*/
118	cmp	r1, #0x20		/* test if set			*/
119	bne	readspdbit
120
121setupsdram:
122	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
123	ldrb	r1, [r0, #3]		/* number of row address lines		*/
124	ldrb	r2, [r0, #4]		/* number of column address lines	*/
125	ldrb	r3, [r0, #5]		/* number of banks			*/
126	ldrb	r4, [r0, #31]		/* module bank density			*/
127	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
128	mov	r5, r5, ASL#2		/* size in MB				*/
129	mov	r0, #CM_BASE		/* reload for later code		*/
130	cmp	r5, #0x10		/* is it 16MB?				*/
131	bne	not16
132	mov	r6, #0x2		/* store size and CAS latency of 2	*/
133	b	writesize
134
135not16:
136	cmp	r5, #0x20		/* is it  32MB? */
137	bne	not32
138	mov	r6, #0x6
139	b	writesize
140
141not32:
142	cmp	r5, #0x40		/* is it  64MB? */
143	bne	not64
144	mov	r6, #0xa
145	b	writesize
146
147not64:
148	cmp	r5, #0x80		/* is it 128MB? */
149	bne	not128
150	mov	r6, #0xe
151	b	writesize
152
153not128:
154	/* if it is none of these sizes then it is either 256MB, or
155	 * there is no SDRAM fitted so default to 256MB
156	 */
157	mov	r6, #0x12
158
159writesize:
160	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
161	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
162	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
163	orr	r6, r6, r3		/* OR in size and CAS latency	 */
164	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
165
166#endif /* #ifdef CONFIG_CM_SPD_DETECT */
167
168	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
169
170#ifdef	CONFIG_CM_REMAP
171	/* CM remap bit is operational
172	 * - use it to map writeable memory at 0x00000000, in place of flash
173	 */
174.globl cm_remap
175cm_remap:
176	stmfd	r13!,{r4-r10,lr}
177
178	mov	r0, #CM_BASE
179	ldr	r1, [r0, #OS_CTRL]
180	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
181	str	r1, [r0, #OS_CTRL]
182
183	/* Now 0x00000000 is writeable, replace the vectors	*/
184	ldr	r0, =_start	/* r0 <- start of vectors	*/
185	add	r2, r0, #64	/* r2 <- past vectors	*/
186	sub	r1,r1,r1		/* destination 0x00000000	*/
187
188copy_vec:
189	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
190	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
191	cmp	r0, r2			/* until source end address [r2]	*/
192	ble	copy_vec
193
194	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
195
196#endif /* #ifdef CONFIG_CM_REMAP */
197