1 /*
2  * (C) Copyright 2002
3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4  * Marius Groeger <mgroeger@sysgo.de>
5  *
6  * (C) Copyright 2002
7  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8  *
9  * (C) Copyright 2003
10  * Texas Instruments, <www.ti.com>
11  * Kshitij Gupta <Kshitij@ti.com>
12  *
13  * (C) Copyright 2004
14  * ARM Ltd.
15  * Philippe Robin, <philippe.robin@arm.com>
16  *
17  * See file CREDITS for list of people who contributed to this
18  * project.
19  *
20  * This program is free software; you can redistribute it and/or
21  * modify it under the terms of the GNU General Public License as
22  * published by the Free Software Foundation; either version 2 of
23  * the License, or (at your option) any later version.
24  *
25  * This program is distributed in the hope that it will be useful,
26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
28  * GNU General Public License for more details.
29  *
30  * You should have received a copy of the GNU General Public License
31  * along with this program; if not, write to the Free Software
32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33  * MA 02111-1307 USA
34  */
35 
36 #include <common.h>
37 #include <netdev.h>
38 #include <asm/io.h>
39 #include "arm-ebi.h"
40 #include "integrator-sc.h"
41 
42 DECLARE_GLOBAL_DATA_PTR;
43 
44 void peripheral_power_enable (void);
45 
46 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
47 void show_boot_progress(int progress)
48 {
49 	printf("Boot reached stage %d\n", progress);
50 }
51 #endif
52 
53 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
54 
55 /*
56  * Miscellaneous platform dependent initialisations
57  */
58 
59 int board_init (void)
60 {
61 	u32 val;
62 
63 	/* arch number of Integrator Board */
64 #ifdef CONFIG_ARCH_CINTEGRATOR
65 	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
66 #else
67 	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
68 #endif
69 
70 	/* adress of boot parameters */
71 	gd->bd->bi_boot_params = 0x00000100;
72 
73 	gd->flags = 0;
74 
75 #ifdef CONFIG_CM_REMAP
76 extern void cm_remap(void);
77 	cm_remap();	/* remaps writeable memory to 0x00000000 */
78 #endif
79 
80 #ifdef CONFIG_ARCH_CINTEGRATOR
81 	/*
82 	 * Flash protection on the Integrator/CP is in a simple register
83 	 */
84 	val = readl(CP_FLASHPROG);
85 	val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
86 	writel(val, CP_FLASHPROG);
87 #else
88 	/*
89 	 * The Integrator/AP has some special protection mechanisms
90 	 * for the external memories, first the External Bus Interface (EBI)
91 	 * then the system controller (SC).
92 	 *
93 	 * The system comes up with the flash memory non-writable and
94 	 * configuration locked. If we want U-Boot to be used for flash
95 	 * access we cannot have the flash memory locked.
96 	 */
97 	writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
98 	val = readl(EBI_BASE + EBI_CSR1_REG);
99 	val &= EBI_CSR_WREN_MASK;
100 	val |= EBI_CSR_WREN_ENABLE;
101 	writel(val, EBI_BASE + EBI_CSR1_REG);
102 	writel(0, EBI_BASE + EBI_LOCK_REG);
103 
104 	/*
105 	 * Set up the system controller to remove write protection from
106 	 * the flash memory and enable Vpp
107 	 */
108 	writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
109 #endif
110 
111 	icache_enable ();
112 
113 	return 0;
114 }
115 
116 int misc_init_r (void)
117 {
118 #ifdef CONFIG_PCI
119 	pci_init();
120 #endif
121 	setenv("verify", "n");
122 	return (0);
123 }
124 
125 /*
126  * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
127  * from there, which means we cannot test the RAM underneath the ROM at this
128  * point. It will be unmapped later on, when we are executing from the
129  * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
130  * RAM on higher addresses works fine.
131  */
132 #define REMAPPED_FLASH_SZ 0x40000
133 
134 int dram_init (void)
135 {
136 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
137 #ifdef CONFIG_CM_SPD_DETECT
138 	{
139 extern void dram_query(void);
140 	u32 cm_reg_sdram;
141 	u32 sdram_shift;
142 
143 	dram_query();	/* Assembler accesses to CM registers */
144 			/* Queries the SPD values	      */
145 
146 	/* Obtain the SDRAM size from the CM SDRAM register */
147 
148 	cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
149 	/*   Register	      SDRAM size
150 	 *
151 	 *   0xXXXXXXbbb000bb	 16 MB
152 	 *   0xXXXXXXbbb001bb	 32 MB
153 	 *   0xXXXXXXbbb010bb	 64 MB
154 	 *   0xXXXXXXbbb011bb	128 MB
155 	 *   0xXXXXXXbbb100bb	256 MB
156 	 *
157 	 */
158 	sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
159 	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
160 				    REMAPPED_FLASH_SZ,
161 				    0x01000000 << sdram_shift);
162 	}
163 #else
164 	gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
165 				    REMAPPED_FLASH_SZ,
166 				    PHYS_SDRAM_1_SIZE);
167 #endif /* CM_SPD_DETECT */
168 	/* We only have one bank of RAM, set it to whatever was detected */
169 	gd->bd->bi_dram[0].size	 = gd->ram_size;
170 
171 	return 0;
172 }
173 
174 #ifdef CONFIG_CMD_NET
175 int board_eth_init(bd_t *bis)
176 {
177 	int rc = 0;
178 #ifdef CONFIG_SMC91111
179 	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
180 #endif
181 	rc += pci_eth_init(bis);
182 	return rc;
183 }
184 #endif
185