1 /* 2 * (C) Copyright 2002 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 8 * 9 * (C) Copyright 2003 10 * Texas Instruments, <www.ti.com> 11 * Kshitij Gupta <Kshitij@ti.com> 12 * 13 * (C) Copyright 2004 14 * ARM Ltd. 15 * Philippe Robin, <philippe.robin@arm.com> 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 20 #include <common.h> 21 #include <dm.h> 22 #include <netdev.h> 23 #include <asm/io.h> 24 #include <dm/platform_data/serial_pl01x.h> 25 #include "arm-ebi.h" 26 #include "integrator-sc.h" 27 #include <asm/mach-types.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 static const struct pl01x_serial_platdata serial_platdata = { 32 .base = 0x16000000, 33 #ifdef CONFIG_ARCH_CINTEGRATOR 34 .type = TYPE_PL011, 35 .clock = 14745600, 36 #else 37 .type = TYPE_PL010, 38 .clock = 0, /* Not used for PL010 */ 39 #endif 40 }; 41 42 U_BOOT_DEVICE(integrator_serials) = { 43 .name = "serial_pl01x", 44 .platdata = &serial_platdata, 45 }; 46 47 void peripheral_power_enable (void); 48 49 #if defined(CONFIG_SHOW_BOOT_PROGRESS) 50 void show_boot_progress(int progress) 51 { 52 printf("Boot reached stage %d\n", progress); 53 } 54 #endif 55 56 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) 57 58 /* 59 * Miscellaneous platform dependent initialisations 60 */ 61 62 int board_init (void) 63 { 64 u32 val; 65 66 /* arch number of Integrator Board */ 67 #ifdef CONFIG_ARCH_CINTEGRATOR 68 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; 69 #else 70 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR; 71 #endif 72 73 /* adress of boot parameters */ 74 gd->bd->bi_boot_params = 0x00000100; 75 76 #ifdef CONFIG_CM_REMAP 77 extern void cm_remap(void); 78 cm_remap(); /* remaps writeable memory to 0x00000000 */ 79 #endif 80 81 #ifdef CONFIG_ARCH_CINTEGRATOR 82 /* 83 * Flash protection on the Integrator/CP is in a simple register 84 */ 85 val = readl(CP_FLASHPROG); 86 val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN); 87 writel(val, CP_FLASHPROG); 88 #else 89 /* 90 * The Integrator/AP has some special protection mechanisms 91 * for the external memories, first the External Bus Interface (EBI) 92 * then the system controller (SC). 93 * 94 * The system comes up with the flash memory non-writable and 95 * configuration locked. If we want U-Boot to be used for flash 96 * access we cannot have the flash memory locked. 97 */ 98 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); 99 val = readl(EBI_BASE + EBI_CSR1_REG); 100 val &= EBI_CSR_WREN_MASK; 101 val |= EBI_CSR_WREN_ENABLE; 102 writel(val, EBI_BASE + EBI_CSR1_REG); 103 writel(0, EBI_BASE + EBI_LOCK_REG); 104 105 /* 106 * Set up the system controller to remove write protection from 107 * the flash memory and enable Vpp 108 */ 109 writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS); 110 #endif 111 112 icache_enable (); 113 114 return 0; 115 } 116 117 int misc_init_r (void) 118 { 119 env_set("verify", "n"); 120 return (0); 121 } 122 123 /* 124 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot 125 * from there, which means we cannot test the RAM underneath the ROM at this 126 * point. It will be unmapped later on, when we are executing from the 127 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the 128 * RAM on higher addresses works fine. 129 */ 130 #define REMAPPED_FLASH_SZ 0x40000 131 132 int dram_init (void) 133 { 134 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 135 #ifdef CONFIG_CM_SPD_DETECT 136 { 137 extern void dram_query(void); 138 u32 cm_reg_sdram; 139 u32 sdram_shift; 140 141 dram_query(); /* Assembler accesses to CM registers */ 142 /* Queries the SPD values */ 143 144 /* Obtain the SDRAM size from the CM SDRAM register */ 145 146 cm_reg_sdram = readl(CM_BASE + OS_SDRAM); 147 /* Register SDRAM size 148 * 149 * 0xXXXXXXbbb000bb 16 MB 150 * 0xXXXXXXbbb001bb 32 MB 151 * 0xXXXXXXbbb010bb 64 MB 152 * 0xXXXXXXbbb011bb 128 MB 153 * 0xXXXXXXbbb100bb 256 MB 154 * 155 */ 156 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; 157 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + 158 REMAPPED_FLASH_SZ, 159 0x01000000 << sdram_shift); 160 } 161 #else 162 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + 163 REMAPPED_FLASH_SZ, 164 PHYS_SDRAM_1_SIZE); 165 #endif /* CM_SPD_DETECT */ 166 /* We only have one bank of RAM, set it to whatever was detected */ 167 gd->bd->bi_dram[0].size = gd->ram_size; 168 169 return 0; 170 } 171 172 #ifdef CONFIG_CMD_NET 173 int board_eth_init(bd_t *bis) 174 { 175 int rc = 0; 176 #ifdef CONFIG_SMC91111 177 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); 178 #endif 179 rc += pci_eth_init(bis); 180 return rc; 181 } 182 #endif 183