1 /* 2 * (C) Copyright 2002 3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Marius Groeger <mgroeger@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> 8 * 9 * (C) Copyright 2003 10 * Texas Instruments, <www.ti.com> 11 * Kshitij Gupta <Kshitij@ti.com> 12 * 13 * (C) Copyright 2004 14 * ARM Ltd. 15 * Philippe Robin, <philippe.robin@arm.com> 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 20 #include <common.h> 21 #include <netdev.h> 22 #include <asm/io.h> 23 #include "arm-ebi.h" 24 #include "integrator-sc.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 void peripheral_power_enable (void); 29 30 #if defined(CONFIG_SHOW_BOOT_PROGRESS) 31 void show_boot_progress(int progress) 32 { 33 printf("Boot reached stage %d\n", progress); 34 } 35 #endif 36 37 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) 38 39 /* 40 * Miscellaneous platform dependent initialisations 41 */ 42 43 int board_init (void) 44 { 45 u32 val; 46 47 /* arch number of Integrator Board */ 48 #ifdef CONFIG_ARCH_CINTEGRATOR 49 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR; 50 #else 51 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR; 52 #endif 53 54 /* adress of boot parameters */ 55 gd->bd->bi_boot_params = 0x00000100; 56 57 #ifdef CONFIG_CM_REMAP 58 extern void cm_remap(void); 59 cm_remap(); /* remaps writeable memory to 0x00000000 */ 60 #endif 61 62 #ifdef CONFIG_ARCH_CINTEGRATOR 63 /* 64 * Flash protection on the Integrator/CP is in a simple register 65 */ 66 val = readl(CP_FLASHPROG); 67 val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN); 68 writel(val, CP_FLASHPROG); 69 #else 70 /* 71 * The Integrator/AP has some special protection mechanisms 72 * for the external memories, first the External Bus Interface (EBI) 73 * then the system controller (SC). 74 * 75 * The system comes up with the flash memory non-writable and 76 * configuration locked. If we want U-Boot to be used for flash 77 * access we cannot have the flash memory locked. 78 */ 79 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG); 80 val = readl(EBI_BASE + EBI_CSR1_REG); 81 val &= EBI_CSR_WREN_MASK; 82 val |= EBI_CSR_WREN_ENABLE; 83 writel(val, EBI_BASE + EBI_CSR1_REG); 84 writel(0, EBI_BASE + EBI_LOCK_REG); 85 86 /* 87 * Set up the system controller to remove write protection from 88 * the flash memory and enable Vpp 89 */ 90 writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS); 91 #endif 92 93 icache_enable (); 94 95 return 0; 96 } 97 98 int misc_init_r (void) 99 { 100 setenv("verify", "n"); 101 return (0); 102 } 103 104 /* 105 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot 106 * from there, which means we cannot test the RAM underneath the ROM at this 107 * point. It will be unmapped later on, when we are executing from the 108 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the 109 * RAM on higher addresses works fine. 110 */ 111 #define REMAPPED_FLASH_SZ 0x40000 112 113 int dram_init (void) 114 { 115 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 116 #ifdef CONFIG_CM_SPD_DETECT 117 { 118 extern void dram_query(void); 119 u32 cm_reg_sdram; 120 u32 sdram_shift; 121 122 dram_query(); /* Assembler accesses to CM registers */ 123 /* Queries the SPD values */ 124 125 /* Obtain the SDRAM size from the CM SDRAM register */ 126 127 cm_reg_sdram = readl(CM_BASE + OS_SDRAM); 128 /* Register SDRAM size 129 * 130 * 0xXXXXXXbbb000bb 16 MB 131 * 0xXXXXXXbbb001bb 32 MB 132 * 0xXXXXXXbbb010bb 64 MB 133 * 0xXXXXXXbbb011bb 128 MB 134 * 0xXXXXXXbbb100bb 256 MB 135 * 136 */ 137 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; 138 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + 139 REMAPPED_FLASH_SZ, 140 0x01000000 << sdram_shift); 141 } 142 #else 143 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE + 144 REMAPPED_FLASH_SZ, 145 PHYS_SDRAM_1_SIZE); 146 #endif /* CM_SPD_DETECT */ 147 /* We only have one bank of RAM, set it to whatever was detected */ 148 gd->bd->bi_dram[0].size = gd->ram_size; 149 150 return 0; 151 } 152 153 #ifdef CONFIG_CMD_NET 154 int board_eth_init(bd_t *bis) 155 { 156 int rc = 0; 157 #ifdef CONFIG_SMC91111 158 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); 159 #endif 160 rc += pci_eth_init(bis); 161 return rc; 162 } 163 #endif 164