1 /* 2 * (C) Copyright 2011 3 * Linaro 4 * Linus Walleij <linus.walleij@linaro.org> 5 * Register definitions for the System Controller (SC) and 6 * the similar "CP Controller" found in the ARM Integrator/AP and 7 * Integrator/CP reference designs 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #ifndef __ARM_SC_H 29 #define __ARM_SC_H 30 31 #define SC_BASE 0x11000000 32 33 /* 34 * The system controller registers 35 */ 36 #define SC_ID_OFFSET 0x00 37 #define SC_OSC_OFFSET 0x04 38 /* Setting this bit switches to 25 MHz mode, clear means 33 MHz */ 39 #define SC_OSC_DIVXY (1 << 8) 40 #define SC_CTRLS_OFFSET 0x08 41 #define SC_CTRLC_OFFSET 0x0C 42 /* Set bits by writing CTRLS, clear bits by writing CTRLC */ 43 #define SC_CTRL_SOFTRESET (1 << 0) 44 #define SC_CTRL_FLASHVPP (1 << 1) 45 #define SC_CTRL_FLASHWP (1 << 2) 46 #define SC_CTRL_UART1DTR (1 << 4) 47 #define SC_CTRL_UART1RTS (1 << 5) 48 #define SC_CTRL_UART0DTR (1 << 6) 49 #define SC_CTRL_UART0RTS (1 << 7) 50 #define SC_DEC_OFFSET 0x10 51 #define SC_ARB_OFFSET 0x14 52 #define SC_PCI_OFFSET 0x18 53 #define SC_PCI_PCIEN (1 << 0) 54 #define SC_PCI_PCIBINT_CLR (1 << 1) 55 #define SC_LOCK_OFFSET 0x1C 56 #define SC_LBFADDR_OFFSET 0x20 57 #define SC_LBFCODE_OFFSET 0x24 58 59 #define SC_ID (SC_BASE + SC_ID_OFFSET) 60 #define SC_OSC (SC_BASE + SC_OSC_OFFSET) 61 #define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET) 62 #define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET) 63 #define SC_DEC (SC_BASE + SC_DEC_OFFSET) 64 #define SC_ARB (SC_BASE + SC_ARB_OFFSET) 65 #define SC_PCI (SC_BASE + SC_PCI_OFFSET) 66 #define SC_LOCK (SC_BASE + SC_LOCK_OFFSET) 67 #define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET) 68 #define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET) 69 70 /* 71 * The Integrator/CP as a smaller set of registers, at a different 72 * offset - probably not to disturb old software. 73 */ 74 75 #define CP_BASE 0xCB000000 76 77 #define CP_IDFIELD_OFFSET 0x00 78 #define CP_FLASHPROG_OFFSET 0x04 79 #define CP_FLASHPROG_FLVPPEN (1 << 0) 80 #define CP_FLASHPROG_FLWREN (1 << 1) 81 #define CP_FLASHPROG_FLASHSIZE (1 << 2) 82 #define CP_FLASHPROG_EXTRABANK (1 << 3) 83 #define CP_INTREG_OFFSET 0x08 84 #define CP_DECODE_OFFSET 0x0C 85 86 #define CP_IDFIELD (CP_BASE + CP_ID_OFFSET) 87 #define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET) 88 #define CP_INTREG (CP_BASE + CP_INTREG_OFFSET) 89 #define CP_DECODE (CP_BASE + CP_DECODE_OFFSET) 90 91 #endif 92