1 /* 2 * (C) Copyright 2011 3 * Linaro 4 * Linus Walleij <linus.walleij@linaro.org> 5 * Register definitions for the External Bus Interface (EBI) 6 * found in the ARM Integrator AP and CP reference designs 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __ARM_EBI_H 12 #define __ARM_EBI_H 13 14 #define EBI_BASE 0x12000000 15 16 #define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */ 17 #define EBI_CSR1_REG 0x04 /* CS1 = Flash */ 18 #define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */ 19 #define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */ 20 /* 21 * The four upper bits are the waitstates for each chip select 22 * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles 23 */ 24 #define EBI_CSR_WAIT_MASK 0xF0 25 /* Whether memory is synchronous or asynchronous */ 26 #define EBI_CSR_SYNC_MASK 0xF7 27 #define EBI_CSR_ASYNC 0x00 28 #define EBI_CSR_SYNC 0x08 29 /* Whether memory is write enabled or not */ 30 #define EBI_CSR_WREN_MASK 0xFB 31 #define EBI_CSR_WREN_DISABLE 0x00 32 #define EBI_CSR_WREN_ENABLE 0x04 33 /* Memory bit width for each chip select */ 34 #define EBI_CSR_MEMSIZE_MASK 0xFC 35 #define EBI_CSR_MEMSIZE_8BIT 0x00 36 #define EBI_CSR_MEMSIZE_16BIT 0x01 37 #define EBI_CSR_MEMSIZE_32BIT 0x02 38 39 /* 40 * The lock register need to be written with 0xa05f before anything in the 41 * EBI can be changed. 42 */ 43 #define EBI_LOCK_REG 0x20 44 #define EBI_UNLOCK_MAGIC 0xA05F 45 46 #endif 47