1 /*
2  * (C) Copyright 2011
3  * Linaro
4  * Linus Walleij <linus.walleij@linaro.org>
5  * Register definitions for the External Bus Interface (EBI)
6  * found in the ARM Integrator AP and CP reference designs
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; either version 2 of
14  * the License, or (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24  * MA 02111-1307 USA
25  */
26 
27 #ifndef __ARM_EBI_H
28 #define __ARM_EBI_H
29 
30 #define EBI_BASE		0x12000000
31 
32 #define EBI_CSR0_REG		0x00 /* CS0 = Boot ROM */
33 #define EBI_CSR1_REG		0x04 /* CS1 = Flash */
34 #define EBI_CSR2_REG		0x08 /* CS2 = SSRAM */
35 #define EBI_CSR3_REG		0x0C /* CS3 = Expansion memory */
36 /*
37  * The four upper bits are the waitstates for each chip select
38  * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
39  */
40 #define EBI_CSR_WAIT_MASK	0xF0
41 /* Whether memory is synchronous or asynchronous */
42 #define EBI_CSR_SYNC_MASK	0xF7
43 #define EBI_CSR_ASYNC		0x00
44 #define EBI_CSR_SYNC		0x08
45 /* Whether memory is write enabled or not */
46 #define EBI_CSR_WREN_MASK	0xFB
47 #define EBI_CSR_WREN_DISABLE	0x00
48 #define EBI_CSR_WREN_ENABLE	0x04
49 /* Memory bit width for each chip select */
50 #define EBI_CSR_MEMSIZE_MASK	0xFC
51 #define EBI_CSR_MEMSIZE_8BIT	0x00
52 #define EBI_CSR_MEMSIZE_16BIT	0x01
53 #define EBI_CSR_MEMSIZE_32BIT	0x02
54 
55 /*
56  * The lock register need to be written with 0xa05f before anything in the
57  * EBI can be changed.
58  */
59 #define EBI_LOCK_REG		0x20
60 #define EBI_UNLOCK_MAGIC	0xA05F
61 
62 #endif
63