1*701ed16eSLinus Walleij /* 2*701ed16eSLinus Walleij * (C) Copyright 2011 3*701ed16eSLinus Walleij * Linaro 4*701ed16eSLinus Walleij * Linus Walleij <linus.walleij@linaro.org> 5*701ed16eSLinus Walleij * Register definitions for the External Bus Interface (EBI) 6*701ed16eSLinus Walleij * found in the ARM Integrator AP and CP reference designs 7*701ed16eSLinus Walleij * 8*701ed16eSLinus Walleij * See file CREDITS for list of people who contributed to this 9*701ed16eSLinus Walleij * project. 10*701ed16eSLinus Walleij * 11*701ed16eSLinus Walleij * This program is free software; you can redistribute it and/or 12*701ed16eSLinus Walleij * modify it under the terms of the GNU General Public License as 13*701ed16eSLinus Walleij * published by the Free Software Foundation; either version 2 of 14*701ed16eSLinus Walleij * the License, or (at your option) any later version. 15*701ed16eSLinus Walleij * 16*701ed16eSLinus Walleij * This program is distributed in the hope that it will be useful, 17*701ed16eSLinus Walleij * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*701ed16eSLinus Walleij * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*701ed16eSLinus Walleij * GNU General Public License for more details. 20*701ed16eSLinus Walleij * 21*701ed16eSLinus Walleij * You should have received a copy of the GNU General Public License 22*701ed16eSLinus Walleij * along with this program; if not, write to the Free Software 23*701ed16eSLinus Walleij * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24*701ed16eSLinus Walleij * MA 02111-1307 USA 25*701ed16eSLinus Walleij */ 26*701ed16eSLinus Walleij 27*701ed16eSLinus Walleij #ifndef __ARM_EBI_H 28*701ed16eSLinus Walleij #define __ARM_EBI_H 29*701ed16eSLinus Walleij 30*701ed16eSLinus Walleij #define EBI_BASE 0x12000000 31*701ed16eSLinus Walleij 32*701ed16eSLinus Walleij #define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */ 33*701ed16eSLinus Walleij #define EBI_CSR1_REG 0x04 /* CS1 = Flash */ 34*701ed16eSLinus Walleij #define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */ 35*701ed16eSLinus Walleij #define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */ 36*701ed16eSLinus Walleij /* 37*701ed16eSLinus Walleij * The four upper bits are the waitstates for each chip select 38*701ed16eSLinus Walleij * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles 39*701ed16eSLinus Walleij */ 40*701ed16eSLinus Walleij #define EBI_CSR_WAIT_MASK 0xF0 41*701ed16eSLinus Walleij /* Whether memory is synchronous or asynchronous */ 42*701ed16eSLinus Walleij #define EBI_CSR_SYNC_MASK 0xF7 43*701ed16eSLinus Walleij #define EBI_CSR_ASYNC 0x00 44*701ed16eSLinus Walleij #define EBI_CSR_SYNC 0x08 45*701ed16eSLinus Walleij /* Whether memory is write enabled or not */ 46*701ed16eSLinus Walleij #define EBI_CSR_WREN_MASK 0xFB 47*701ed16eSLinus Walleij #define EBI_CSR_WREN_DISABLE 0x00 48*701ed16eSLinus Walleij #define EBI_CSR_WREN_ENABLE 0x04 49*701ed16eSLinus Walleij /* Memory bit width for each chip select */ 50*701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_MASK 0xFC 51*701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_8BIT 0x00 52*701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_16BIT 0x01 53*701ed16eSLinus Walleij #define EBI_CSR_MEMSIZE_32BIT 0x02 54*701ed16eSLinus Walleij 55*701ed16eSLinus Walleij /* 56*701ed16eSLinus Walleij * The lock register need to be written with 0xa05f before anything in the 57*701ed16eSLinus Walleij * EBI can be changed. 58*701ed16eSLinus Walleij */ 59*701ed16eSLinus Walleij #define EBI_LOCK_REG 0x20 60*701ed16eSLinus Walleij #define EBI_UNLOCK_MAGIC 0xA05F 61*701ed16eSLinus Walleij 62*701ed16eSLinus Walleij #endif 63