1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2bcc05c7aStrem /* 3bcc05c7aStrem * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 4bcc05c7aStrem */ 5bcc05c7aStrem 6bcc05c7aStrem #ifndef __APF27_H 7bcc05c7aStrem #define __APF27_H 8bcc05c7aStrem 9bcc05c7aStrem /* FPGA program pin configuration */ 10bcc05c7aStrem #define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ 11bcc05c7aStrem #define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ 12bcc05c7aStrem #define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ 13bcc05c7aStrem #define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ 14bcc05c7aStrem #define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ 15bcc05c7aStrem #define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ 16bcc05c7aStrem #define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ 17bcc05c7aStrem #define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ 18bcc05c7aStrem #define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ 19bcc05c7aStrem #define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ 20bcc05c7aStrem #define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ 21bcc05c7aStrem 22bcc05c7aStrem /* MMC pin */ 23bcc05c7aStrem #define PC_PWRON (GPIO_PORTF | 16) 24bcc05c7aStrem 25bcc05c7aStrem /* 26bcc05c7aStrem * MPU CLOCK source before PLL 27bcc05c7aStrem * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) 28bcc05c7aStrem */ 29bcc05c7aStrem #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ 30bcc05c7aStrem #define ACFG_MPCTL1_VAL 0 31bcc05c7aStrem #define CONFIG_MPLL_FREQ 399 32bcc05c7aStrem 33bcc05c7aStrem #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ 34bcc05c7aStrem 35bcc05c7aStrem /* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ 36bcc05c7aStrem #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ 37bcc05c7aStrem #define ACFG_SPCTL1_VAL 0 38bcc05c7aStrem #define CONFIG_SPLL_FREQ 300 /* MHz */ 39bcc05c7aStrem 40bcc05c7aStrem /* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ 41bcc05c7aStrem #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ 42bcc05c7aStrem 43bcc05c7aStrem /* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ 44bcc05c7aStrem #define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ 45bcc05c7aStrem 46bcc05c7aStrem #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ 47bcc05c7aStrem #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ 48bcc05c7aStrem #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ 49bcc05c7aStrem #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ 50bcc05c7aStrem #define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ 51bcc05c7aStrem #define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ 52bcc05c7aStrem #define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ 53bcc05c7aStrem #define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ 54bcc05c7aStrem #define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ 55bcc05c7aStrem #define CONFIG_CLK0_EN 1 /* CLK0 enabled */ 56bcc05c7aStrem 57bcc05c7aStrem /* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ 58bcc05c7aStrem #define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ 59bcc05c7aStrem 60bcc05c7aStrem /* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ 61bcc05c7aStrem #define CONFIG_USB_FREQ 60 /* 60 MHz */ 62bcc05c7aStrem 63bcc05c7aStrem /* 64bcc05c7aStrem * SDRAM 65bcc05c7aStrem */ 66bcc05c7aStrem #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 67bcc05c7aStrem /* micron 64MB */ 68bcc05c7aStrem #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 69bcc05c7aStrem * column address bits 70bcc05c7aStrem */ 71bcc05c7aStrem #define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 72bcc05c7aStrem * row address bits 73bcc05c7aStrem */ 74bcc05c7aStrem #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 75bcc05c7aStrem * 2=4096 3=8192 refresh 76bcc05c7aStrem */ 77bcc05c7aStrem #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 78bcc05c7aStrem * down delay 79bcc05c7aStrem */ 80bcc05c7aStrem #define ACFG_SDRAM_W2R_DELAY 1 /* write to read 81bcc05c7aStrem * cycle delay > 0 82bcc05c7aStrem */ 83bcc05c7aStrem #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 84bcc05c7aStrem #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 85bcc05c7aStrem * cycle delay 1..4 86bcc05c7aStrem */ 87bcc05c7aStrem #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 88bcc05c7aStrem * SDRAM: 0=1ck 1=2ck 89bcc05c7aStrem */ 90bcc05c7aStrem #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 91bcc05c7aStrem #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 92bcc05c7aStrem #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 93bcc05c7aStrem #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 94bcc05c7aStrem * refresh to command) 95bcc05c7aStrem */ 96bcc05c7aStrem #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 97bcc05c7aStrem * estimated fo CL=1 98bcc05c7aStrem * 0=force 3 for lpddr 99bcc05c7aStrem */ 100bcc05c7aStrem #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 101bcc05c7aStrem * 3=Eighth 4=Sixteenth 102bcc05c7aStrem */ 103bcc05c7aStrem #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 104bcc05c7aStrem * 2=quater 3=Eighth 105bcc05c7aStrem */ 106bcc05c7aStrem #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 107bcc05c7aStrem #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 108bcc05c7aStrem * 0 = Burst mode 109bcc05c7aStrem */ 110bcc05c7aStrem #endif 111bcc05c7aStrem 112bcc05c7aStrem #if (ACFG_SDRAM_MBYTE_SYZE == 128) 113bcc05c7aStrem /* micron 128MB */ 114bcc05c7aStrem #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 115bcc05c7aStrem * column address bits 116bcc05c7aStrem */ 117bcc05c7aStrem #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 118bcc05c7aStrem * row address bits 119bcc05c7aStrem */ 120bcc05c7aStrem #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 121bcc05c7aStrem * 2=4096 3=8192 refresh 122bcc05c7aStrem */ 123bcc05c7aStrem #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 124bcc05c7aStrem * down delay 125bcc05c7aStrem */ 126bcc05c7aStrem #define ACFG_SDRAM_W2R_DELAY 1 /* write to read 127bcc05c7aStrem * cycle delay > 0 128bcc05c7aStrem */ 129bcc05c7aStrem #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 130bcc05c7aStrem #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 131bcc05c7aStrem * cycle delay 1..4 132bcc05c7aStrem */ 133bcc05c7aStrem #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 134bcc05c7aStrem * SDRAM: 0=1ck 1=2ck 135bcc05c7aStrem */ 136bcc05c7aStrem #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 137bcc05c7aStrem #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 138bcc05c7aStrem #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 139bcc05c7aStrem #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 140bcc05c7aStrem * refresh to command) 141bcc05c7aStrem */ 142bcc05c7aStrem #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 143bcc05c7aStrem * estimated fo CL=1 144bcc05c7aStrem * 0=force 3 for lpddr 145bcc05c7aStrem */ 146bcc05c7aStrem #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 147bcc05c7aStrem * 3=Eighth 4=Sixteenth 148bcc05c7aStrem */ 149bcc05c7aStrem #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 150bcc05c7aStrem * 2=quater 3=Eighth 151bcc05c7aStrem */ 152bcc05c7aStrem #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 153bcc05c7aStrem #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 154bcc05c7aStrem * 0 = Burst mode 155bcc05c7aStrem */ 156bcc05c7aStrem #endif 157bcc05c7aStrem 158bcc05c7aStrem #if (ACFG_SDRAM_MBYTE_SYZE == 256) 159bcc05c7aStrem /* micron 256MB */ 160bcc05c7aStrem #define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 161bcc05c7aStrem * column address bits 162bcc05c7aStrem */ 163bcc05c7aStrem #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 164bcc05c7aStrem * row address bits 165bcc05c7aStrem */ 166bcc05c7aStrem #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 167bcc05c7aStrem * 2=4096 3=8192 refresh 168bcc05c7aStrem */ 169bcc05c7aStrem #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 170bcc05c7aStrem * down delay 171bcc05c7aStrem */ 172bcc05c7aStrem #define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle 173bcc05c7aStrem * delay > 0 174bcc05c7aStrem */ 175bcc05c7aStrem #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 176bcc05c7aStrem #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 177bcc05c7aStrem * cycle delay 1..4 178bcc05c7aStrem */ 179bcc05c7aStrem #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 180bcc05c7aStrem * SDRAM: 0=1ck 1=2ck 181bcc05c7aStrem */ 182bcc05c7aStrem #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 183bcc05c7aStrem #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 184bcc05c7aStrem #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 185bcc05c7aStrem #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 186bcc05c7aStrem * refresh to command) 187bcc05c7aStrem */ 188bcc05c7aStrem #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 189bcc05c7aStrem * estimated fo CL=1 190bcc05c7aStrem * 0=force 3 for lpddr 191bcc05c7aStrem */ 192bcc05c7aStrem #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 193bcc05c7aStrem * 3=Eighth 4=Sixteenth 194bcc05c7aStrem */ 195bcc05c7aStrem #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 196bcc05c7aStrem * 1=half 197bcc05c7aStrem * 2=quater 198bcc05c7aStrem * 3=Eighth 199bcc05c7aStrem */ 200bcc05c7aStrem #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 201bcc05c7aStrem #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 202bcc05c7aStrem * 0 = Burst mode 203bcc05c7aStrem */ 204bcc05c7aStrem #endif 205bcc05c7aStrem 206bcc05c7aStrem /* 207bcc05c7aStrem * External interface 208bcc05c7aStrem */ 209bcc05c7aStrem /* 210bcc05c7aStrem * CSCRxU_VAL: 211bcc05c7aStrem * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 212bcc05c7aStrem * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | 213bcc05c7aStrem * 214bcc05c7aStrem * 15| x x | x x x x x x | x | x x x x | x x x x |0 215bcc05c7aStrem * | CNC | WSC |EW | WWS | EDC | 216bcc05c7aStrem * 217bcc05c7aStrem * CSCRxL_VAL: 218bcc05c7aStrem * 31| x x x x | x x x x | x x x x | x x x x |16 219bcc05c7aStrem * | OEA | OEN | EBWA | EBWN | 220bcc05c7aStrem * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 221bcc05c7aStrem * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| 222bcc05c7aStrem * 223bcc05c7aStrem * CSCRxA_VAL: 224bcc05c7aStrem * 31| x x x x | x x x x | x x x x | x x x x |16 225bcc05c7aStrem * | EBRA | EBRN | RWA | RWN | 226bcc05c7aStrem * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 227bcc05c7aStrem * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| 228bcc05c7aStrem */ 229bcc05c7aStrem 230bcc05c7aStrem /* CS0 configuration for 16 bit nor flash */ 231bcc05c7aStrem #define ACFG_CS0U_VAL 0x0000CC03 232bcc05c7aStrem #define ACFG_CS0L_VAL 0xa0330D01 233bcc05c7aStrem #define ACFG_CS0A_VAL 0x00220800 234bcc05c7aStrem 235bcc05c7aStrem #define ACFG_CS1U_VAL 0x00000f00 236bcc05c7aStrem #define ACFG_CS1L_VAL 0x00000D01 237bcc05c7aStrem #define ACFG_CS1A_VAL 0 238bcc05c7aStrem 239bcc05c7aStrem #define ACFG_CS2U_VAL 0 240bcc05c7aStrem #define ACFG_CS2L_VAL 0 241bcc05c7aStrem #define ACFG_CS2A_VAL 0 242bcc05c7aStrem 243bcc05c7aStrem #define ACFG_CS3U_VAL 0 244bcc05c7aStrem #define ACFG_CS3L_VAL 0 245bcc05c7aStrem #define ACFG_CS3A_VAL 0 246bcc05c7aStrem 247bcc05c7aStrem #define ACFG_CS4U_VAL 0 248bcc05c7aStrem #define ACFG_CS4L_VAL 0 249bcc05c7aStrem #define ACFG_CS4A_VAL 0 250bcc05c7aStrem 251bcc05c7aStrem /* FPGA 16 bit data bus */ 252bcc05c7aStrem #define ACFG_CS5U_VAL 0x00000600 253bcc05c7aStrem #define ACFG_CS5L_VAL 0x00000D01 254bcc05c7aStrem #define ACFG_CS5A_VAL 0 255bcc05c7aStrem 256bcc05c7aStrem #define ACFG_EIM_VAL 0x00002200 257bcc05c7aStrem 258bcc05c7aStrem 259bcc05c7aStrem /* 260bcc05c7aStrem * FPGA specific settings 261bcc05c7aStrem */ 262bcc05c7aStrem 263bcc05c7aStrem /* CLKO */ 264bcc05c7aStrem #define ACFG_CCSR_VAL 0x00000305 265bcc05c7aStrem /* drive strength CLKO set to 2 */ 266bcc05c7aStrem #define ACFG_DSCR10_VAL 0x00020000 267bcc05c7aStrem /* drive strength A1..A12 set to 2 */ 268bcc05c7aStrem #define ACFG_DSCR3_VAL 0x02AAAAA8 269bcc05c7aStrem /* drive strength ctrl */ 270bcc05c7aStrem #define ACFG_DSCR7_VAL 0x00020880 271bcc05c7aStrem /* drive strength data */ 272bcc05c7aStrem #define ACFG_DSCR2_VAL 0xAAAAAAAA 273bcc05c7aStrem 274bcc05c7aStrem 275bcc05c7aStrem /* 276bcc05c7aStrem * Default configuration for GPIOs and peripherals 277bcc05c7aStrem */ 278bcc05c7aStrem #define ACFG_DDIR_A_VAL 0x00000000 279bcc05c7aStrem #define ACFG_OCR1_A_VAL 0x00000000 280bcc05c7aStrem #define ACFG_OCR2_A_VAL 0x00000000 281bcc05c7aStrem #define ACFG_ICFA1_A_VAL 0xFFFFFFFF 282bcc05c7aStrem #define ACFG_ICFA2_A_VAL 0xFFFFFFFF 283bcc05c7aStrem #define ACFG_ICFB1_A_VAL 0xFFFFFFFF 284bcc05c7aStrem #define ACFG_ICFB2_A_VAL 0xFFFFFFFF 285bcc05c7aStrem #define ACFG_DR_A_VAL 0x00000000 286bcc05c7aStrem #define ACFG_GIUS_A_VAL 0xFFFFFFFF 287bcc05c7aStrem #define ACFG_ICR1_A_VAL 0x00000000 288bcc05c7aStrem #define ACFG_ICR2_A_VAL 0x00000000 289bcc05c7aStrem #define ACFG_IMR_A_VAL 0x00000000 290bcc05c7aStrem #define ACFG_GPR_A_VAL 0x00000000 291bcc05c7aStrem #define ACFG_PUEN_A_VAL 0xFFFFFFFF 292bcc05c7aStrem 293bcc05c7aStrem #define ACFG_DDIR_B_VAL 0x00000000 294bcc05c7aStrem #define ACFG_OCR1_B_VAL 0x00000000 295bcc05c7aStrem #define ACFG_OCR2_B_VAL 0x00000000 296bcc05c7aStrem #define ACFG_ICFA1_B_VAL 0xFFFFFFFF 297bcc05c7aStrem #define ACFG_ICFA2_B_VAL 0xFFFFFFFF 298bcc05c7aStrem #define ACFG_ICFB1_B_VAL 0xFFFFFFFF 299bcc05c7aStrem #define ACFG_ICFB2_B_VAL 0xFFFFFFFF 300bcc05c7aStrem #define ACFG_DR_B_VAL 0x00000000 301bcc05c7aStrem #define ACFG_GIUS_B_VAL 0xFF3FFFF0 302bcc05c7aStrem #define ACFG_ICR1_B_VAL 0x00000000 303bcc05c7aStrem #define ACFG_ICR2_B_VAL 0x00000000 304bcc05c7aStrem #define ACFG_IMR_B_VAL 0x00000000 305bcc05c7aStrem #define ACFG_GPR_B_VAL 0x00000000 306bcc05c7aStrem #define ACFG_PUEN_B_VAL 0xFFFFFFFF 307bcc05c7aStrem 308bcc05c7aStrem #define ACFG_DDIR_C_VAL 0x00000000 309bcc05c7aStrem #define ACFG_OCR1_C_VAL 0x00000000 310bcc05c7aStrem #define ACFG_OCR2_C_VAL 0x00000000 311bcc05c7aStrem #define ACFG_ICFA1_C_VAL 0xFFFFFFFF 312bcc05c7aStrem #define ACFG_ICFA2_C_VAL 0xFFFFFFFF 313bcc05c7aStrem #define ACFG_ICFB1_C_VAL 0xFFFFFFFF 314bcc05c7aStrem #define ACFG_ICFB2_C_VAL 0xFFFFFFFF 315bcc05c7aStrem #define ACFG_DR_C_VAL 0x00000000 316bcc05c7aStrem #define ACFG_GIUS_C_VAL 0xFFFFC07F 317bcc05c7aStrem #define ACFG_ICR1_C_VAL 0x00000000 318bcc05c7aStrem #define ACFG_ICR2_C_VAL 0x00000000 319bcc05c7aStrem #define ACFG_IMR_C_VAL 0x00000000 320bcc05c7aStrem #define ACFG_GPR_C_VAL 0x00000000 321bcc05c7aStrem #define ACFG_PUEN_C_VAL 0xFFFFFF87 322bcc05c7aStrem 323bcc05c7aStrem #define ACFG_DDIR_D_VAL 0x00000000 324bcc05c7aStrem #define ACFG_OCR1_D_VAL 0x00000000 325bcc05c7aStrem #define ACFG_OCR2_D_VAL 0x00000000 326bcc05c7aStrem #define ACFG_ICFA1_D_VAL 0xFFFFFFFF 327bcc05c7aStrem #define ACFG_ICFA2_D_VAL 0xFFFFFFFF 328bcc05c7aStrem #define ACFG_ICFB1_D_VAL 0xFFFFFFFF 329bcc05c7aStrem #define ACFG_ICFB2_D_VAL 0xFFFFFFFF 330bcc05c7aStrem #define ACFG_DR_D_VAL 0x00000000 331bcc05c7aStrem #define ACFG_GIUS_D_VAL 0xFFFFFFFF 332bcc05c7aStrem #define ACFG_ICR1_D_VAL 0x00000000 333bcc05c7aStrem #define ACFG_ICR2_D_VAL 0x00000000 334bcc05c7aStrem #define ACFG_IMR_D_VAL 0x00000000 335bcc05c7aStrem #define ACFG_GPR_D_VAL 0x00000000 336bcc05c7aStrem #define ACFG_PUEN_D_VAL 0xFFFFFFFF 337bcc05c7aStrem 338bcc05c7aStrem #define ACFG_DDIR_E_VAL 0x00000000 339bcc05c7aStrem #define ACFG_OCR1_E_VAL 0x00000000 340bcc05c7aStrem #define ACFG_OCR2_E_VAL 0x00000000 341bcc05c7aStrem #define ACFG_ICFA1_E_VAL 0xFFFFFFFF 342bcc05c7aStrem #define ACFG_ICFA2_E_VAL 0xFFFFFFFF 343bcc05c7aStrem #define ACFG_ICFB1_E_VAL 0xFFFFFFFF 344bcc05c7aStrem #define ACFG_ICFB2_E_VAL 0xFFFFFFFF 345bcc05c7aStrem #define ACFG_DR_E_VAL 0x00000000 346bcc05c7aStrem #define ACFG_GIUS_E_VAL 0xFCFFCCF8 347bcc05c7aStrem #define ACFG_ICR1_E_VAL 0x00000000 348bcc05c7aStrem #define ACFG_ICR2_E_VAL 0x00000000 349bcc05c7aStrem #define ACFG_IMR_E_VAL 0x00000000 350bcc05c7aStrem #define ACFG_GPR_E_VAL 0x00000000 351bcc05c7aStrem #define ACFG_PUEN_E_VAL 0xFFFFFFFF 352bcc05c7aStrem 353bcc05c7aStrem #define ACFG_DDIR_F_VAL 0x00000000 354bcc05c7aStrem #define ACFG_OCR1_F_VAL 0x00000000 355bcc05c7aStrem #define ACFG_OCR2_F_VAL 0x00000000 356bcc05c7aStrem #define ACFG_ICFA1_F_VAL 0xFFFFFFFF 357bcc05c7aStrem #define ACFG_ICFA2_F_VAL 0xFFFFFFFF 358bcc05c7aStrem #define ACFG_ICFB1_F_VAL 0xFFFFFFFF 359bcc05c7aStrem #define ACFG_ICFB2_F_VAL 0xFFFFFFFF 360bcc05c7aStrem #define ACFG_DR_F_VAL 0x00000000 361bcc05c7aStrem #define ACFG_GIUS_F_VAL 0xFF7F8000 362bcc05c7aStrem #define ACFG_ICR1_F_VAL 0x00000000 363bcc05c7aStrem #define ACFG_ICR2_F_VAL 0x00000000 364bcc05c7aStrem #define ACFG_IMR_F_VAL 0x00000000 365bcc05c7aStrem #define ACFG_GPR_F_VAL 0x00000000 366bcc05c7aStrem #define ACFG_PUEN_F_VAL 0xFFFFFFFF 367bcc05c7aStrem 368bcc05c7aStrem /* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ 369bcc05c7aStrem #define ACFG_GPCR_VAL 0x0003000F 370bcc05c7aStrem 371bcc05c7aStrem #define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN 372bcc05c7aStrem 373bcc05c7aStrem /* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ 374bcc05c7aStrem #if (CONFIG_NR_DRAM_BANKS == 1) 375bcc05c7aStrem #define ACFG_FMCR_VAL 0xFFFFFFF9 376bcc05c7aStrem #elif (CONFIG_NR_DRAM_BANKS == 2) 377bcc05c7aStrem #define ACFG_FMCR_VAL 0xFFFFFFFB 378bcc05c7aStrem #endif 379bcc05c7aStrem 380bcc05c7aStrem #define ACFG_AIPI1_PSR0_VAL 0x20040304 381bcc05c7aStrem #define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB 382bcc05c7aStrem #define ACFG_AIPI2_PSR0_VAL 0x00000000 383bcc05c7aStrem #define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF 384bcc05c7aStrem 385bcc05c7aStrem /* PCCR enable DMA FEC I2C1 IIM SDHC1 */ 386bcc05c7aStrem #define ACFG_PCCR0_VAL 0x05070410 387bcc05c7aStrem #define ACFG_PCCR1_VAL 0xA14A0608 388bcc05c7aStrem 389bcc05c7aStrem /* 390bcc05c7aStrem * From here, there should not be any user configuration. 391bcc05c7aStrem * All Equations are automatic 392bcc05c7aStrem */ 393bcc05c7aStrem 394bcc05c7aStrem /* fixme none integer value (7.5ns) => 2*hclock = 15ns */ 395bcc05c7aStrem #define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ 396bcc05c7aStrem 397bcc05c7aStrem /* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ 398bcc05c7aStrem #define CSCR_MASK 0x0300800D 399bcc05c7aStrem 400bcc05c7aStrem #define ACFG_CSCR_VAL \ 401bcc05c7aStrem (CSCR_MASK \ 402bcc05c7aStrem |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ 403bcc05c7aStrem |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ 404bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) 405bcc05c7aStrem 406bcc05c7aStrem /* SSIx CLKO NFC H264 MSHC */ 407bcc05c7aStrem #define ACFG_PCDR0_VAL\ 408bcc05c7aStrem (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ 409bcc05c7aStrem |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ 410bcc05c7aStrem |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ 411bcc05c7aStrem |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ 412bcc05c7aStrem |(((CONFIG_CLK0_DIV)&0x07)<<22)\ 413bcc05c7aStrem |(((CONFIG_CLK0_EN)&0x01)<<25)\ 414bcc05c7aStrem |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) 415bcc05c7aStrem 416bcc05c7aStrem /* PERCLKx */ 417bcc05c7aStrem #define ACFG_PCDR1_VAL\ 418bcc05c7aStrem (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ 419bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ 420bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ 421bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) 422bcc05c7aStrem 423bcc05c7aStrem /* SDRAM controller programming Values */ 424bcc05c7aStrem #if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ 425bcc05c7aStrem (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) 426bcc05c7aStrem #define REG_FIELD_SCL_VAL 3 427bcc05c7aStrem #define REG_FIELD_SCLIMX_VAL 0 428bcc05c7aStrem #else 429bcc05c7aStrem #define REG_FIELD_SCL_VAL\ 430bcc05c7aStrem ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ 431bcc05c7aStrem ACFG_2XHCLK_LGTH) 432bcc05c7aStrem #define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL 433bcc05c7aStrem #endif 434bcc05c7aStrem 435bcc05c7aStrem #if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) 436bcc05c7aStrem #define REG_FIELD_SRC_VAL 0 437bcc05c7aStrem #else 438bcc05c7aStrem #define REG_FIELD_SRC_VAL\ 439bcc05c7aStrem ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 440bcc05c7aStrem ACFG_2XHCLK_LGTH) 441bcc05c7aStrem #endif 442bcc05c7aStrem 443bcc05c7aStrem /* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ 444bcc05c7aStrem #define REG_ESDCTL_BASE_CONFIG (0x80020485\ 445bcc05c7aStrem | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ 446bcc05c7aStrem | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ 447bcc05c7aStrem | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) 448bcc05c7aStrem 449bcc05c7aStrem #define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) 450bcc05c7aStrem #define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) 451bcc05c7aStrem #define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) 452bcc05c7aStrem #define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) 453bcc05c7aStrem 454bcc05c7aStrem /* ESDRAMC Configuration Registers : force CL=3 to lpddr */ 455bcc05c7aStrem #define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ 456bcc05c7aStrem | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ 457bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ 458bcc05c7aStrem | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ 459bcc05c7aStrem | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ 460bcc05c7aStrem ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ 461bcc05c7aStrem | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ 462bcc05c7aStrem | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ 463bcc05c7aStrem | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 464bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ 465bcc05c7aStrem | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 466bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ 467bcc05c7aStrem | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ 468bcc05c7aStrem | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 469bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ 470bcc05c7aStrem | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) 471bcc05c7aStrem 472bcc05c7aStrem /* Issue Mode register Command to SDRAM */ 473bcc05c7aStrem #define ACFG_SDRAM_MODE_REGISTER_VAL\ 474bcc05c7aStrem ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ 475bcc05c7aStrem | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ 476bcc05c7aStrem | ((0)<<(3)) /* sequentiql access */ \ 477bcc05c7aStrem /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) 478bcc05c7aStrem 479bcc05c7aStrem /* Issue Extended Mode register Command to SDRAM */ 480bcc05c7aStrem #define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ 481bcc05c7aStrem ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ 482bcc05c7aStrem | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ 483bcc05c7aStrem | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) 484bcc05c7aStrem 485bcc05c7aStrem /* Issue Precharge all Command to SDRAM */ 486bcc05c7aStrem #define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) 487bcc05c7aStrem 488bcc05c7aStrem #endif /* __APF27_H */ 489