1*bcc05c7aStrem /* 2*bcc05c7aStrem * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 3*bcc05c7aStrem * 4*bcc05c7aStrem * SPDX-License-Identifier: GPL-2.0+ 5*bcc05c7aStrem */ 6*bcc05c7aStrem 7*bcc05c7aStrem #ifndef __APF27_H 8*bcc05c7aStrem #define __APF27_H 9*bcc05c7aStrem 10*bcc05c7aStrem /* FPGA program pin configuration */ 11*bcc05c7aStrem #define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ 12*bcc05c7aStrem #define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ 13*bcc05c7aStrem #define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ 14*bcc05c7aStrem #define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ 15*bcc05c7aStrem #define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ 16*bcc05c7aStrem #define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ 17*bcc05c7aStrem #define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ 18*bcc05c7aStrem #define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ 19*bcc05c7aStrem #define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ 20*bcc05c7aStrem #define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ 21*bcc05c7aStrem #define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ 22*bcc05c7aStrem 23*bcc05c7aStrem /* MMC pin */ 24*bcc05c7aStrem #define PC_PWRON (GPIO_PORTF | 16) 25*bcc05c7aStrem 26*bcc05c7aStrem /* 27*bcc05c7aStrem * MPU CLOCK source before PLL 28*bcc05c7aStrem * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) 29*bcc05c7aStrem */ 30*bcc05c7aStrem #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ 31*bcc05c7aStrem #define ACFG_MPCTL1_VAL 0 32*bcc05c7aStrem #define CONFIG_MPLL_FREQ 399 33*bcc05c7aStrem 34*bcc05c7aStrem #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ 35*bcc05c7aStrem 36*bcc05c7aStrem /* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ 37*bcc05c7aStrem #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ 38*bcc05c7aStrem #define ACFG_SPCTL1_VAL 0 39*bcc05c7aStrem #define CONFIG_SPLL_FREQ 300 /* MHz */ 40*bcc05c7aStrem 41*bcc05c7aStrem /* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ 42*bcc05c7aStrem #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ 43*bcc05c7aStrem 44*bcc05c7aStrem /* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ 45*bcc05c7aStrem #define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ 46*bcc05c7aStrem 47*bcc05c7aStrem #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ 48*bcc05c7aStrem #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ 49*bcc05c7aStrem #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ 50*bcc05c7aStrem #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ 51*bcc05c7aStrem #define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ 52*bcc05c7aStrem #define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ 53*bcc05c7aStrem #define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ 54*bcc05c7aStrem #define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ 55*bcc05c7aStrem #define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ 56*bcc05c7aStrem #define CONFIG_CLK0_EN 1 /* CLK0 enabled */ 57*bcc05c7aStrem 58*bcc05c7aStrem /* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ 59*bcc05c7aStrem #define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ 60*bcc05c7aStrem 61*bcc05c7aStrem /* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ 62*bcc05c7aStrem #define CONFIG_USB_FREQ 60 /* 60 MHz */ 63*bcc05c7aStrem 64*bcc05c7aStrem /* 65*bcc05c7aStrem * SDRAM 66*bcc05c7aStrem */ 67*bcc05c7aStrem #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 68*bcc05c7aStrem /* micron 64MB */ 69*bcc05c7aStrem #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 70*bcc05c7aStrem * column address bits 71*bcc05c7aStrem */ 72*bcc05c7aStrem #define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 73*bcc05c7aStrem * row address bits 74*bcc05c7aStrem */ 75*bcc05c7aStrem #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 76*bcc05c7aStrem * 2=4096 3=8192 refresh 77*bcc05c7aStrem */ 78*bcc05c7aStrem #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 79*bcc05c7aStrem * down delay 80*bcc05c7aStrem */ 81*bcc05c7aStrem #define ACFG_SDRAM_W2R_DELAY 1 /* write to read 82*bcc05c7aStrem * cycle delay > 0 83*bcc05c7aStrem */ 84*bcc05c7aStrem #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 85*bcc05c7aStrem #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 86*bcc05c7aStrem * cycle delay 1..4 87*bcc05c7aStrem */ 88*bcc05c7aStrem #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 89*bcc05c7aStrem * SDRAM: 0=1ck 1=2ck 90*bcc05c7aStrem */ 91*bcc05c7aStrem #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 92*bcc05c7aStrem #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 93*bcc05c7aStrem #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 94*bcc05c7aStrem #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 95*bcc05c7aStrem * refresh to command) 96*bcc05c7aStrem */ 97*bcc05c7aStrem #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 98*bcc05c7aStrem * estimated fo CL=1 99*bcc05c7aStrem * 0=force 3 for lpddr 100*bcc05c7aStrem */ 101*bcc05c7aStrem #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 102*bcc05c7aStrem * 3=Eighth 4=Sixteenth 103*bcc05c7aStrem */ 104*bcc05c7aStrem #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 105*bcc05c7aStrem * 2=quater 3=Eighth 106*bcc05c7aStrem */ 107*bcc05c7aStrem #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 108*bcc05c7aStrem #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 109*bcc05c7aStrem * 0 = Burst mode 110*bcc05c7aStrem */ 111*bcc05c7aStrem #endif 112*bcc05c7aStrem 113*bcc05c7aStrem #if (ACFG_SDRAM_MBYTE_SYZE == 128) 114*bcc05c7aStrem /* micron 128MB */ 115*bcc05c7aStrem #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 116*bcc05c7aStrem * column address bits 117*bcc05c7aStrem */ 118*bcc05c7aStrem #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 119*bcc05c7aStrem * row address bits 120*bcc05c7aStrem */ 121*bcc05c7aStrem #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 122*bcc05c7aStrem * 2=4096 3=8192 refresh 123*bcc05c7aStrem */ 124*bcc05c7aStrem #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 125*bcc05c7aStrem * down delay 126*bcc05c7aStrem */ 127*bcc05c7aStrem #define ACFG_SDRAM_W2R_DELAY 1 /* write to read 128*bcc05c7aStrem * cycle delay > 0 129*bcc05c7aStrem */ 130*bcc05c7aStrem #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 131*bcc05c7aStrem #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 132*bcc05c7aStrem * cycle delay 1..4 133*bcc05c7aStrem */ 134*bcc05c7aStrem #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 135*bcc05c7aStrem * SDRAM: 0=1ck 1=2ck 136*bcc05c7aStrem */ 137*bcc05c7aStrem #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 138*bcc05c7aStrem #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 139*bcc05c7aStrem #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 140*bcc05c7aStrem #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 141*bcc05c7aStrem * refresh to command) 142*bcc05c7aStrem */ 143*bcc05c7aStrem #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 144*bcc05c7aStrem * estimated fo CL=1 145*bcc05c7aStrem * 0=force 3 for lpddr 146*bcc05c7aStrem */ 147*bcc05c7aStrem #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 148*bcc05c7aStrem * 3=Eighth 4=Sixteenth 149*bcc05c7aStrem */ 150*bcc05c7aStrem #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 151*bcc05c7aStrem * 2=quater 3=Eighth 152*bcc05c7aStrem */ 153*bcc05c7aStrem #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 154*bcc05c7aStrem #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 155*bcc05c7aStrem * 0 = Burst mode 156*bcc05c7aStrem */ 157*bcc05c7aStrem #endif 158*bcc05c7aStrem 159*bcc05c7aStrem #if (ACFG_SDRAM_MBYTE_SYZE == 256) 160*bcc05c7aStrem /* micron 256MB */ 161*bcc05c7aStrem #define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 162*bcc05c7aStrem * column address bits 163*bcc05c7aStrem */ 164*bcc05c7aStrem #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 165*bcc05c7aStrem * row address bits 166*bcc05c7aStrem */ 167*bcc05c7aStrem #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 168*bcc05c7aStrem * 2=4096 3=8192 refresh 169*bcc05c7aStrem */ 170*bcc05c7aStrem #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 171*bcc05c7aStrem * down delay 172*bcc05c7aStrem */ 173*bcc05c7aStrem #define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle 174*bcc05c7aStrem * delay > 0 175*bcc05c7aStrem */ 176*bcc05c7aStrem #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 177*bcc05c7aStrem #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 178*bcc05c7aStrem * cycle delay 1..4 179*bcc05c7aStrem */ 180*bcc05c7aStrem #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 181*bcc05c7aStrem * SDRAM: 0=1ck 1=2ck 182*bcc05c7aStrem */ 183*bcc05c7aStrem #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 184*bcc05c7aStrem #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 185*bcc05c7aStrem #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 186*bcc05c7aStrem #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 187*bcc05c7aStrem * refresh to command) 188*bcc05c7aStrem */ 189*bcc05c7aStrem #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 190*bcc05c7aStrem * estimated fo CL=1 191*bcc05c7aStrem * 0=force 3 for lpddr 192*bcc05c7aStrem */ 193*bcc05c7aStrem #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 194*bcc05c7aStrem * 3=Eighth 4=Sixteenth 195*bcc05c7aStrem */ 196*bcc05c7aStrem #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 197*bcc05c7aStrem * 1=half 198*bcc05c7aStrem * 2=quater 199*bcc05c7aStrem * 3=Eighth 200*bcc05c7aStrem */ 201*bcc05c7aStrem #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 202*bcc05c7aStrem #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 203*bcc05c7aStrem * 0 = Burst mode 204*bcc05c7aStrem */ 205*bcc05c7aStrem #endif 206*bcc05c7aStrem 207*bcc05c7aStrem /* 208*bcc05c7aStrem * External interface 209*bcc05c7aStrem */ 210*bcc05c7aStrem /* 211*bcc05c7aStrem * CSCRxU_VAL: 212*bcc05c7aStrem * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 213*bcc05c7aStrem * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | 214*bcc05c7aStrem * 215*bcc05c7aStrem * 15| x x | x x x x x x | x | x x x x | x x x x |0 216*bcc05c7aStrem * | CNC | WSC |EW | WWS | EDC | 217*bcc05c7aStrem * 218*bcc05c7aStrem * CSCRxL_VAL: 219*bcc05c7aStrem * 31| x x x x | x x x x | x x x x | x x x x |16 220*bcc05c7aStrem * | OEA | OEN | EBWA | EBWN | 221*bcc05c7aStrem * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 222*bcc05c7aStrem * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| 223*bcc05c7aStrem * 224*bcc05c7aStrem * CSCRxA_VAL: 225*bcc05c7aStrem * 31| x x x x | x x x x | x x x x | x x x x |16 226*bcc05c7aStrem * | EBRA | EBRN | RWA | RWN | 227*bcc05c7aStrem * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 228*bcc05c7aStrem * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| 229*bcc05c7aStrem */ 230*bcc05c7aStrem 231*bcc05c7aStrem /* CS0 configuration for 16 bit nor flash */ 232*bcc05c7aStrem #define ACFG_CS0U_VAL 0x0000CC03 233*bcc05c7aStrem #define ACFG_CS0L_VAL 0xa0330D01 234*bcc05c7aStrem #define ACFG_CS0A_VAL 0x00220800 235*bcc05c7aStrem 236*bcc05c7aStrem #define ACFG_CS1U_VAL 0x00000f00 237*bcc05c7aStrem #define ACFG_CS1L_VAL 0x00000D01 238*bcc05c7aStrem #define ACFG_CS1A_VAL 0 239*bcc05c7aStrem 240*bcc05c7aStrem #define ACFG_CS2U_VAL 0 241*bcc05c7aStrem #define ACFG_CS2L_VAL 0 242*bcc05c7aStrem #define ACFG_CS2A_VAL 0 243*bcc05c7aStrem 244*bcc05c7aStrem #define ACFG_CS3U_VAL 0 245*bcc05c7aStrem #define ACFG_CS3L_VAL 0 246*bcc05c7aStrem #define ACFG_CS3A_VAL 0 247*bcc05c7aStrem 248*bcc05c7aStrem #define ACFG_CS4U_VAL 0 249*bcc05c7aStrem #define ACFG_CS4L_VAL 0 250*bcc05c7aStrem #define ACFG_CS4A_VAL 0 251*bcc05c7aStrem 252*bcc05c7aStrem /* FPGA 16 bit data bus */ 253*bcc05c7aStrem #define ACFG_CS5U_VAL 0x00000600 254*bcc05c7aStrem #define ACFG_CS5L_VAL 0x00000D01 255*bcc05c7aStrem #define ACFG_CS5A_VAL 0 256*bcc05c7aStrem 257*bcc05c7aStrem #define ACFG_EIM_VAL 0x00002200 258*bcc05c7aStrem 259*bcc05c7aStrem 260*bcc05c7aStrem /* 261*bcc05c7aStrem * FPGA specific settings 262*bcc05c7aStrem */ 263*bcc05c7aStrem 264*bcc05c7aStrem /* CLKO */ 265*bcc05c7aStrem #define ACFG_CCSR_VAL 0x00000305 266*bcc05c7aStrem /* drive strength CLKO set to 2 */ 267*bcc05c7aStrem #define ACFG_DSCR10_VAL 0x00020000 268*bcc05c7aStrem /* drive strength A1..A12 set to 2 */ 269*bcc05c7aStrem #define ACFG_DSCR3_VAL 0x02AAAAA8 270*bcc05c7aStrem /* drive strength ctrl */ 271*bcc05c7aStrem #define ACFG_DSCR7_VAL 0x00020880 272*bcc05c7aStrem /* drive strength data */ 273*bcc05c7aStrem #define ACFG_DSCR2_VAL 0xAAAAAAAA 274*bcc05c7aStrem 275*bcc05c7aStrem 276*bcc05c7aStrem /* 277*bcc05c7aStrem * Default configuration for GPIOs and peripherals 278*bcc05c7aStrem */ 279*bcc05c7aStrem #define ACFG_DDIR_A_VAL 0x00000000 280*bcc05c7aStrem #define ACFG_OCR1_A_VAL 0x00000000 281*bcc05c7aStrem #define ACFG_OCR2_A_VAL 0x00000000 282*bcc05c7aStrem #define ACFG_ICFA1_A_VAL 0xFFFFFFFF 283*bcc05c7aStrem #define ACFG_ICFA2_A_VAL 0xFFFFFFFF 284*bcc05c7aStrem #define ACFG_ICFB1_A_VAL 0xFFFFFFFF 285*bcc05c7aStrem #define ACFG_ICFB2_A_VAL 0xFFFFFFFF 286*bcc05c7aStrem #define ACFG_DR_A_VAL 0x00000000 287*bcc05c7aStrem #define ACFG_GIUS_A_VAL 0xFFFFFFFF 288*bcc05c7aStrem #define ACFG_ICR1_A_VAL 0x00000000 289*bcc05c7aStrem #define ACFG_ICR2_A_VAL 0x00000000 290*bcc05c7aStrem #define ACFG_IMR_A_VAL 0x00000000 291*bcc05c7aStrem #define ACFG_GPR_A_VAL 0x00000000 292*bcc05c7aStrem #define ACFG_PUEN_A_VAL 0xFFFFFFFF 293*bcc05c7aStrem 294*bcc05c7aStrem #define ACFG_DDIR_B_VAL 0x00000000 295*bcc05c7aStrem #define ACFG_OCR1_B_VAL 0x00000000 296*bcc05c7aStrem #define ACFG_OCR2_B_VAL 0x00000000 297*bcc05c7aStrem #define ACFG_ICFA1_B_VAL 0xFFFFFFFF 298*bcc05c7aStrem #define ACFG_ICFA2_B_VAL 0xFFFFFFFF 299*bcc05c7aStrem #define ACFG_ICFB1_B_VAL 0xFFFFFFFF 300*bcc05c7aStrem #define ACFG_ICFB2_B_VAL 0xFFFFFFFF 301*bcc05c7aStrem #define ACFG_DR_B_VAL 0x00000000 302*bcc05c7aStrem #define ACFG_GIUS_B_VAL 0xFF3FFFF0 303*bcc05c7aStrem #define ACFG_ICR1_B_VAL 0x00000000 304*bcc05c7aStrem #define ACFG_ICR2_B_VAL 0x00000000 305*bcc05c7aStrem #define ACFG_IMR_B_VAL 0x00000000 306*bcc05c7aStrem #define ACFG_GPR_B_VAL 0x00000000 307*bcc05c7aStrem #define ACFG_PUEN_B_VAL 0xFFFFFFFF 308*bcc05c7aStrem 309*bcc05c7aStrem #define ACFG_DDIR_C_VAL 0x00000000 310*bcc05c7aStrem #define ACFG_OCR1_C_VAL 0x00000000 311*bcc05c7aStrem #define ACFG_OCR2_C_VAL 0x00000000 312*bcc05c7aStrem #define ACFG_ICFA1_C_VAL 0xFFFFFFFF 313*bcc05c7aStrem #define ACFG_ICFA2_C_VAL 0xFFFFFFFF 314*bcc05c7aStrem #define ACFG_ICFB1_C_VAL 0xFFFFFFFF 315*bcc05c7aStrem #define ACFG_ICFB2_C_VAL 0xFFFFFFFF 316*bcc05c7aStrem #define ACFG_DR_C_VAL 0x00000000 317*bcc05c7aStrem #define ACFG_GIUS_C_VAL 0xFFFFC07F 318*bcc05c7aStrem #define ACFG_ICR1_C_VAL 0x00000000 319*bcc05c7aStrem #define ACFG_ICR2_C_VAL 0x00000000 320*bcc05c7aStrem #define ACFG_IMR_C_VAL 0x00000000 321*bcc05c7aStrem #define ACFG_GPR_C_VAL 0x00000000 322*bcc05c7aStrem #define ACFG_PUEN_C_VAL 0xFFFFFF87 323*bcc05c7aStrem 324*bcc05c7aStrem #define ACFG_DDIR_D_VAL 0x00000000 325*bcc05c7aStrem #define ACFG_OCR1_D_VAL 0x00000000 326*bcc05c7aStrem #define ACFG_OCR2_D_VAL 0x00000000 327*bcc05c7aStrem #define ACFG_ICFA1_D_VAL 0xFFFFFFFF 328*bcc05c7aStrem #define ACFG_ICFA2_D_VAL 0xFFFFFFFF 329*bcc05c7aStrem #define ACFG_ICFB1_D_VAL 0xFFFFFFFF 330*bcc05c7aStrem #define ACFG_ICFB2_D_VAL 0xFFFFFFFF 331*bcc05c7aStrem #define ACFG_DR_D_VAL 0x00000000 332*bcc05c7aStrem #define ACFG_GIUS_D_VAL 0xFFFFFFFF 333*bcc05c7aStrem #define ACFG_ICR1_D_VAL 0x00000000 334*bcc05c7aStrem #define ACFG_ICR2_D_VAL 0x00000000 335*bcc05c7aStrem #define ACFG_IMR_D_VAL 0x00000000 336*bcc05c7aStrem #define ACFG_GPR_D_VAL 0x00000000 337*bcc05c7aStrem #define ACFG_PUEN_D_VAL 0xFFFFFFFF 338*bcc05c7aStrem 339*bcc05c7aStrem #define ACFG_DDIR_E_VAL 0x00000000 340*bcc05c7aStrem #define ACFG_OCR1_E_VAL 0x00000000 341*bcc05c7aStrem #define ACFG_OCR2_E_VAL 0x00000000 342*bcc05c7aStrem #define ACFG_ICFA1_E_VAL 0xFFFFFFFF 343*bcc05c7aStrem #define ACFG_ICFA2_E_VAL 0xFFFFFFFF 344*bcc05c7aStrem #define ACFG_ICFB1_E_VAL 0xFFFFFFFF 345*bcc05c7aStrem #define ACFG_ICFB2_E_VAL 0xFFFFFFFF 346*bcc05c7aStrem #define ACFG_DR_E_VAL 0x00000000 347*bcc05c7aStrem #define ACFG_GIUS_E_VAL 0xFCFFCCF8 348*bcc05c7aStrem #define ACFG_ICR1_E_VAL 0x00000000 349*bcc05c7aStrem #define ACFG_ICR2_E_VAL 0x00000000 350*bcc05c7aStrem #define ACFG_IMR_E_VAL 0x00000000 351*bcc05c7aStrem #define ACFG_GPR_E_VAL 0x00000000 352*bcc05c7aStrem #define ACFG_PUEN_E_VAL 0xFFFFFFFF 353*bcc05c7aStrem 354*bcc05c7aStrem #define ACFG_DDIR_F_VAL 0x00000000 355*bcc05c7aStrem #define ACFG_OCR1_F_VAL 0x00000000 356*bcc05c7aStrem #define ACFG_OCR2_F_VAL 0x00000000 357*bcc05c7aStrem #define ACFG_ICFA1_F_VAL 0xFFFFFFFF 358*bcc05c7aStrem #define ACFG_ICFA2_F_VAL 0xFFFFFFFF 359*bcc05c7aStrem #define ACFG_ICFB1_F_VAL 0xFFFFFFFF 360*bcc05c7aStrem #define ACFG_ICFB2_F_VAL 0xFFFFFFFF 361*bcc05c7aStrem #define ACFG_DR_F_VAL 0x00000000 362*bcc05c7aStrem #define ACFG_GIUS_F_VAL 0xFF7F8000 363*bcc05c7aStrem #define ACFG_ICR1_F_VAL 0x00000000 364*bcc05c7aStrem #define ACFG_ICR2_F_VAL 0x00000000 365*bcc05c7aStrem #define ACFG_IMR_F_VAL 0x00000000 366*bcc05c7aStrem #define ACFG_GPR_F_VAL 0x00000000 367*bcc05c7aStrem #define ACFG_PUEN_F_VAL 0xFFFFFFFF 368*bcc05c7aStrem 369*bcc05c7aStrem /* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ 370*bcc05c7aStrem #define ACFG_GPCR_VAL 0x0003000F 371*bcc05c7aStrem 372*bcc05c7aStrem #define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN 373*bcc05c7aStrem 374*bcc05c7aStrem /* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ 375*bcc05c7aStrem #if (CONFIG_NR_DRAM_BANKS == 1) 376*bcc05c7aStrem #define ACFG_FMCR_VAL 0xFFFFFFF9 377*bcc05c7aStrem #elif (CONFIG_NR_DRAM_BANKS == 2) 378*bcc05c7aStrem #define ACFG_FMCR_VAL 0xFFFFFFFB 379*bcc05c7aStrem #endif 380*bcc05c7aStrem 381*bcc05c7aStrem #define ACFG_AIPI1_PSR0_VAL 0x20040304 382*bcc05c7aStrem #define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB 383*bcc05c7aStrem #define ACFG_AIPI2_PSR0_VAL 0x00000000 384*bcc05c7aStrem #define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF 385*bcc05c7aStrem 386*bcc05c7aStrem /* PCCR enable DMA FEC I2C1 IIM SDHC1 */ 387*bcc05c7aStrem #define ACFG_PCCR0_VAL 0x05070410 388*bcc05c7aStrem #define ACFG_PCCR1_VAL 0xA14A0608 389*bcc05c7aStrem 390*bcc05c7aStrem /* 391*bcc05c7aStrem * From here, there should not be any user configuration. 392*bcc05c7aStrem * All Equations are automatic 393*bcc05c7aStrem */ 394*bcc05c7aStrem 395*bcc05c7aStrem /* fixme none integer value (7.5ns) => 2*hclock = 15ns */ 396*bcc05c7aStrem #define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ 397*bcc05c7aStrem 398*bcc05c7aStrem /* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ 399*bcc05c7aStrem #define CSCR_MASK 0x0300800D 400*bcc05c7aStrem 401*bcc05c7aStrem #define ACFG_CSCR_VAL \ 402*bcc05c7aStrem (CSCR_MASK \ 403*bcc05c7aStrem |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ 404*bcc05c7aStrem |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ 405*bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) 406*bcc05c7aStrem 407*bcc05c7aStrem /* SSIx CLKO NFC H264 MSHC */ 408*bcc05c7aStrem #define ACFG_PCDR0_VAL\ 409*bcc05c7aStrem (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ 410*bcc05c7aStrem |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ 411*bcc05c7aStrem |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ 412*bcc05c7aStrem |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ 413*bcc05c7aStrem |(((CONFIG_CLK0_DIV)&0x07)<<22)\ 414*bcc05c7aStrem |(((CONFIG_CLK0_EN)&0x01)<<25)\ 415*bcc05c7aStrem |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) 416*bcc05c7aStrem 417*bcc05c7aStrem /* PERCLKx */ 418*bcc05c7aStrem #define ACFG_PCDR1_VAL\ 419*bcc05c7aStrem (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ 420*bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ 421*bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ 422*bcc05c7aStrem |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) 423*bcc05c7aStrem 424*bcc05c7aStrem /* SDRAM controller programming Values */ 425*bcc05c7aStrem #if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ 426*bcc05c7aStrem (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) 427*bcc05c7aStrem #define REG_FIELD_SCL_VAL 3 428*bcc05c7aStrem #define REG_FIELD_SCLIMX_VAL 0 429*bcc05c7aStrem #else 430*bcc05c7aStrem #define REG_FIELD_SCL_VAL\ 431*bcc05c7aStrem ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ 432*bcc05c7aStrem ACFG_2XHCLK_LGTH) 433*bcc05c7aStrem #define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL 434*bcc05c7aStrem #endif 435*bcc05c7aStrem 436*bcc05c7aStrem #if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) 437*bcc05c7aStrem #define REG_FIELD_SRC_VAL 0 438*bcc05c7aStrem #else 439*bcc05c7aStrem #define REG_FIELD_SRC_VAL\ 440*bcc05c7aStrem ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 441*bcc05c7aStrem ACFG_2XHCLK_LGTH) 442*bcc05c7aStrem #endif 443*bcc05c7aStrem 444*bcc05c7aStrem /* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ 445*bcc05c7aStrem #define REG_ESDCTL_BASE_CONFIG (0x80020485\ 446*bcc05c7aStrem | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ 447*bcc05c7aStrem | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ 448*bcc05c7aStrem | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) 449*bcc05c7aStrem 450*bcc05c7aStrem #define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) 451*bcc05c7aStrem #define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) 452*bcc05c7aStrem #define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) 453*bcc05c7aStrem #define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) 454*bcc05c7aStrem 455*bcc05c7aStrem /* ESDRAMC Configuration Registers : force CL=3 to lpddr */ 456*bcc05c7aStrem #define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ 457*bcc05c7aStrem | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ 458*bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ 459*bcc05c7aStrem | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ 460*bcc05c7aStrem | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ 461*bcc05c7aStrem ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ 462*bcc05c7aStrem | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ 463*bcc05c7aStrem | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ 464*bcc05c7aStrem | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 465*bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ 466*bcc05c7aStrem | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 467*bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ 468*bcc05c7aStrem | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ 469*bcc05c7aStrem | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 470*bcc05c7aStrem ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ 471*bcc05c7aStrem | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) 472*bcc05c7aStrem 473*bcc05c7aStrem /* Issue Mode register Command to SDRAM */ 474*bcc05c7aStrem #define ACFG_SDRAM_MODE_REGISTER_VAL\ 475*bcc05c7aStrem ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ 476*bcc05c7aStrem | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ 477*bcc05c7aStrem | ((0)<<(3)) /* sequentiql access */ \ 478*bcc05c7aStrem /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) 479*bcc05c7aStrem 480*bcc05c7aStrem /* Issue Extended Mode register Command to SDRAM */ 481*bcc05c7aStrem #define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ 482*bcc05c7aStrem ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ 483*bcc05c7aStrem | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ 484*bcc05c7aStrem | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) 485*bcc05c7aStrem 486*bcc05c7aStrem /* Issue Precharge all Command to SDRAM */ 487*bcc05c7aStrem #define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) 488*bcc05c7aStrem 489*bcc05c7aStrem #endif /* __APF27_H */ 490