1 /* 2 * (C) Copyright 2014 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * Based on: 6 * Copyright (C) 2012 Freescale Semiconductor, Inc. 7 * 8 * Author: Fabio Estevam <fabio.estevam@freescale.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <asm/arch/clock.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/iomux.h> 16 #include <asm/arch/mx6-pins.h> 17 #include <asm/errno.h> 18 #include <asm/gpio.h> 19 #include <asm/imx-common/iomux-v3.h> 20 #include <asm/imx-common/boot_mode.h> 21 #include <asm/imx-common/mxc_i2c.h> 22 #include <asm/imx-common/video.h> 23 #include <mmc.h> 24 #include <fsl_esdhc.h> 25 #include <miiphy.h> 26 #include <netdev.h> 27 #include <asm/arch/mxc_hdmi.h> 28 #include <asm/arch/crm_regs.h> 29 #include <linux/fb.h> 30 #include <ipu_pixfmt.h> 31 #include <asm/io.h> 32 #include <asm/arch/sys_proto.h> 33 #include <pwm.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 39 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 40 41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 43 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 44 45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 47 48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ 49 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 50 51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 52 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 53 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 54 55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 56 57 #define DISP_PAD_CTRL (0x10) 58 59 #define ECSPI4_CS1 IMX_GPIO_NR(5, 2) 60 61 #if (CONFIG_SYS_BOARD_VERSION == 1) 62 #include "./aristainetos-v1.c" 63 #elif (CONFIG_SYS_BOARD_VERSION == 2) 64 #include "./aristainetos-v2.c" 65 #endif 66 67 68 struct i2c_pads_info i2c_pad_info1 = { 69 .scl = { 70 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, 71 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, 72 .gp = IMX_GPIO_NR(5, 27) 73 }, 74 .sda = { 75 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, 76 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, 77 .gp = IMX_GPIO_NR(5, 26) 78 } 79 }; 80 81 struct i2c_pads_info i2c_pad_info2 = { 82 .scl = { 83 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, 84 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, 85 .gp = IMX_GPIO_NR(4, 12) 86 }, 87 .sda = { 88 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, 89 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, 90 .gp = IMX_GPIO_NR(4, 13) 91 } 92 }; 93 94 iomux_v3_cfg_t const usdhc1_pads[] = { 95 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 96 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 97 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 98 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 99 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 100 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 101 }; 102 103 int dram_init(void) 104 { 105 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 106 107 return 0; 108 } 109 110 #ifdef CONFIG_FSL_ESDHC 111 struct fsl_esdhc_cfg usdhc_cfg[2] = { 112 {USDHC1_BASE_ADDR}, 113 {USDHC2_BASE_ADDR}, 114 }; 115 116 int board_mmc_getcd(struct mmc *mmc) 117 { 118 return 1; 119 } 120 121 int board_mmc_init(bd_t *bis) 122 { 123 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 124 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 125 #if (CONFIG_SYS_BOARD_VERSION == 2) 126 /* 127 * usdhc2 has a levelshifter on the carrier board Rev. DV1, 128 * that will automatically detect the driving direction. 129 * During initialisation this isn't working correctly, 130 * which causes DAT3 to be driven low towards the SD-card. 131 * This causes a SD-card enetring the SPI-Mode 132 * and therefore getting inaccessible until next power cycle. 133 * As workaround we drive the DAT3 line as GPIO and set it high. 134 * This makes usdhc2 unusable in u-boot, but works for the 135 * initialisation in Linux 136 */ 137 imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 | 138 MUX_PAD_CTRL(NO_PAD_CTRL)); 139 gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); 140 #endif 141 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 142 } 143 #endif 144 145 /* 146 * Do not overwrite the console 147 * Use always serial for U-Boot console 148 */ 149 int overwrite_console(void) 150 { 151 return 1; 152 } 153 154 struct display_info_t const displays[] = { 155 { 156 .bus = -1, 157 .addr = 0, 158 .pixfmt = IPU_PIX_FMT_RGB24, 159 .detect = NULL, 160 .enable = enable_lvds, 161 .mode = { 162 .name = "lb07wv8", 163 .refresh = 60, 164 .xres = 800, 165 .yres = 480, 166 .pixclock = 33246, 167 .left_margin = 88, 168 .right_margin = 88, 169 .upper_margin = 10, 170 .lower_margin = 10, 171 .hsync_len = 80, 172 .vsync_len = 25, 173 .sync = 0, 174 .vmode = FB_VMODE_NONINTERLACED 175 } 176 } 177 #if (CONFIG_SYS_BOARD_VERSION == 2) 178 , { 179 .bus = -1, 180 .addr = 0, 181 .pixfmt = IPU_PIX_FMT_RGB24, 182 .detect = NULL, 183 .enable = enable_spi_display, 184 .mode = { 185 .name = "lg4573", 186 .refresh = 60, 187 .xres = 480, 188 .yres = 800, 189 .pixclock = 37037, 190 .left_margin = 59, 191 .right_margin = 10, 192 .upper_margin = 15, 193 .lower_margin = 15, 194 .hsync_len = 10, 195 .vsync_len = 15, 196 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT | 197 FB_SYNC_VERT_HIGH_ACT, 198 .vmode = FB_VMODE_NONINTERLACED 199 } 200 } 201 #endif 202 }; 203 size_t display_count = ARRAY_SIZE(displays); 204 205 /* no console on this board */ 206 int board_cfb_skip(void) 207 { 208 return 1; 209 } 210 211 iomux_v3_cfg_t nfc_pads[] = { 212 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), 213 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), 214 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), 215 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), 216 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), 217 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), 218 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), 219 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), 220 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 221 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 222 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 223 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 224 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 225 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 226 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 227 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 228 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 229 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 230 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), 231 }; 232 233 static void setup_gpmi_nand(void) 234 { 235 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 236 237 /* config gpmi nand iomux */ 238 imx_iomux_v3_setup_multiple_pads(nfc_pads, 239 ARRAY_SIZE(nfc_pads)); 240 241 /* gate ENFC_CLK_ROOT clock first,before clk source switch */ 242 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 243 244 /* config gpmi and bch clock to 100 MHz */ 245 clrsetbits_le32(&mxc_ccm->cs2cdr, 246 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 247 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 248 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 249 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 250 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 251 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 252 253 /* enable ENFC_CLK_ROOT clock */ 254 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 255 256 /* enable gpmi and bch clock gating */ 257 setbits_le32(&mxc_ccm->CCGR4, 258 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 259 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 260 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 261 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 262 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 263 264 /* enable apbh clock gating */ 265 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 266 } 267 268 int board_init(void) 269 { 270 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 271 272 /* address of boot parameters */ 273 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 274 275 setup_spi(); 276 277 setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 278 &i2c_pad_info1); 279 setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 280 &i2c_pad_info2); 281 setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 282 &i2c_pad_info3); 283 setup_i2c4(); 284 285 /* SPI NOR Flash read only */ 286 gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); 287 gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); 288 gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); 289 290 setup_board_gpio(); 291 setup_gpmi_nand(); 292 setup_board_spi(); 293 294 /* GPIO_1 for USB_OTG_ID */ 295 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); 296 imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); 297 return 0; 298 } 299 300 int checkboard(void) 301 { 302 printf("Board: %s\n", CONFIG_BOARDNAME); 303 return 0; 304 } 305 306 #ifdef CONFIG_USB_EHCI_MX6 307 int board_ehci_hcd_init(int port) 308 { 309 int ret; 310 311 ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr"); 312 if (!ret) 313 gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1); 314 ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr"); 315 if (!ret) 316 gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1); 317 return 0; 318 } 319 320 int board_ehci_power(int port, int on) 321 { 322 if (port) 323 gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); 324 else 325 gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); 326 return 0; 327 } 328 #endif 329