1 /*
2  * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/gxbb.h>
10 #include <asm/arch/sm.h>
11 #include <dm/platdata.h>
12 #include <phy.h>
13 
14 #define EFUSE_SN_OFFSET		20
15 #define EFUSE_SN_SIZE		16
16 #define EFUSE_MAC_OFFSET	52
17 #define EFUSE_MAC_SIZE		6
18 
19 int board_init(void)
20 {
21 	return 0;
22 }
23 
24 static const struct eth_pdata gxbb_eth_pdata = {
25 	.iobase = GXBB_ETH_BASE,
26 	.phy_interface = PHY_INTERFACE_MODE_RGMII,
27 };
28 
29 U_BOOT_DEVICE(meson_eth) = {
30 	.name = "eth_designware",
31 	.platdata = &gxbb_eth_pdata,
32 };
33 
34 int misc_init_r(void)
35 {
36 	u8 mac_addr[EFUSE_MAC_SIZE];
37 	ssize_t len;
38 
39 	/* Select Ethernet function */
40 	setbits_le32(GXBB_PINMUX(6), 0x3fff);
41 
42 	/* Set RGMII mode */
43 	setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
44 				     GXBB_ETH_REG_0_TX_PHASE(1) |
45 				     GXBB_ETH_REG_0_TX_RATIO(4) |
46 				     GXBB_ETH_REG_0_PHY_CLK_EN |
47 				     GXBB_ETH_REG_0_CLK_EN);
48 
49 	/* Enable power and clock gate */
50 	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
51 	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
52 
53 	/* Reset PHY on GPIOZ_14 */
54 	clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
55 	clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
56 	mdelay(10);
57 	setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
58 
59 	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
60 		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
61 					  mac_addr, EFUSE_MAC_SIZE);
62 		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
63 			eth_setenv_enetaddr("ethaddr", mac_addr);
64 	}
65 
66 	return 0;
67 }
68