1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Amazon Kindle Fire (first generation) codename kc1 config 4 * 5 * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> 6 */ 7 8 #ifndef _KC1_H_ 9 #define _KC1_H_ 10 11 #include <asm/arch/mux_omap4.h> 12 13 #define KC1_GPIO_USB_ID 52 14 #define KC1_GPIO_MBID1 173 15 #define KC1_GPIO_MBID0 174 16 #define KC1_GPIO_MBID3 177 17 #define KC1_GPIO_MBID2 178 18 19 const struct pad_conf_entry core_padconf_array[] = { 20 /* GPMC */ 21 { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */ 22 { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */ 23 { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */ 24 { GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */ 25 { GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */ 26 { GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */ 27 { GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */ 28 { GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */ 29 { GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */ 30 { GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */ 31 { GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */ 32 /* CAM */ 33 { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */ 34 { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */ 35 { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */ 36 /* HDQ */ 37 { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */ 38 /* I2C1 */ 39 { I2C1_SCL, (IEN | PTU | M0) }, /* i2c1_scl */ 40 { I2C1_SDA, (IEN | PTU | M0) }, /* i2c1_sda */ 41 /* I2C2 */ 42 { I2C2_SCL, (IEN | PTU | M0) }, /* i2c2_scl */ 43 { I2C2_SDA, (IEN | PTU | M0) }, /* i2c2_sda */ 44 /* I2C3 */ 45 { I2C3_SCL, (IEN | PTU | M0) }, /* i2c3_scl */ 46 { I2C3_SDA, (IEN | PTU | M0) }, /* i2c3_sda */ 47 /* I2C4 */ 48 { I2C4_SCL, (IEN | PTU | M0) }, /* i2c4_scl */ 49 { I2C4_SDA, (IEN | PTU | M0) }, /* i2c4_sda */ 50 /* MCSPI1 */ 51 { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */ 52 { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */ 53 { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */ 54 { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */ 55 { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */ 56 { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */ 57 { MCSPI1_CS3, (IDIS | DIS | M7) }, /* safe_mode */ 58 /* UART3 */ 59 { UART3_CTS_RCTX, (IDIS | DIS | M7) }, /* safe_mode */ 60 { UART3_RTS_SD, (IDIS | DIS | M7) }, /* safe_mode */ 61 { UART3_RX_IRRX, (IEN | DIS | M0) }, /* uart3_rx_irrx */ 62 { UART3_TX_IRTX, (IDIS | DIS | M0) }, /* uart3_tx_irtx */ 63 /* SDMMC5 */ 64 { SDMMC5_CLK, (IEN | PTU | M0) }, /* sdmmc5_clk */ 65 { SDMMC5_CMD, (IEN | PTU | M0) }, /* sdmmc5_cmd */ 66 { SDMMC5_DAT0, (IEN | PTU | M0) }, /* sdmmc5_dat0 */ 67 { SDMMC5_DAT1, (IEN | PTU | M0) }, /* sdmmc5_dat1 */ 68 { SDMMC5_DAT2, (IEN | PTU | M0) }, /* sdmmc5_dat2 */ 69 { SDMMC5_DAT3, (IEN | PTU | M0) }, /* sdmmc5_dat3 */ 70 /* MCSPI4 */ 71 { MCSPI4_CLK, (IEN | DIS | M0) }, /* mcspi4_clk */ 72 { MCSPI4_SIMO, (IEN | DIS | M0) }, /* mcspi4_simo */ 73 { MCSPI4_SOMI, (IEN | DIS | M0) }, /* mcspi4_somi */ 74 { MCSPI4_CS0, (IEN | PTD | M0) }, /* mcspi4_cs0 */ 75 /* UART4 */ 76 { UART4_RX, (IDIS | DIS | M4) }, /* gpio_155 */ 77 { UART4_TX, (IDIS | DIS | M7) }, /* safe_mode */ 78 /* UNIPRO */ 79 { UNIPRO_TX0, (IDIS | DIS | M7) }, /* safe_mode */ 80 { UNIPRO_TY0, (IDIS | DIS | M7) }, /* safe_mode */ 81 { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */ 82 { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */ 83 { UNIPRO_TX2, (IDIS | DIS | M7) }, /* safe_mode */ 84 { UNIPRO_TY2, (IDIS | DIS | M7) }, /* safe_mode */ 85 { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */ 86 { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */ 87 { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */ 88 { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */ 89 { UNIPRO_RX2, (IDIS | DIS | M7) }, /* safe_mode */ 90 { UNIPRO_RY2, (IDIS | DIS | M7) }, /* safe_mode */ 91 /* USBA0_OTG */ 92 { USBA0_OTG_CE, (IDIS | PTD | M0) }, /* usba0_otg_ce */ 93 { USBA0_OTG_DP, (IEN | DIS | M0) }, /* usba0_otg_dp */ 94 { USBA0_OTG_DM, (IEN | DIS | M0) }, /* usba0_otg_dm */ 95 }; 96 97 #endif 98