1 /*
2  * Altera SoCFPGA SDRAM configuration
3  *
4  * SPDX-License-Identifier:	BSD-3-Clause
5  */
6 
7 #ifndef __SOCFPGA_SDRAM_CONFIG_H__
8 #define __SOCFPGA_SDRAM_CONFIG_H__
9 
10 /* SDRAM configuration */
11 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
12 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
13 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
14 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		1
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			1
19 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
20 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
21 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
22 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
23 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
24 #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
25 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
26 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
27 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
28 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
29 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		40
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
35 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			7
36 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
37 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			14
38 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
39 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
40 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
41 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
42 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
44 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
45 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
46 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
47 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
48 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
49 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
50 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
51 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
52 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
53 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
54 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0
55 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
56 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
57 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
58 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
59 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
60 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
61 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
62 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
63 #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
64 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
65 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
66 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
67 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
68 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
69 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
70 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
71 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
72 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
73 #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
74 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
75 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
76 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
77 #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
78 
79 /* Sequencer auto configuration */
80 #define RW_MGR_ACTIVATE_0_AND_1	0x0D
81 #define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
82 #define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
83 #define RW_MGR_ACTIVATE_1	0x0F
84 #define RW_MGR_CLEAR_DQS_ENABLE	0x48
85 #define RW_MGR_GUARANTEED_READ	0x4B
86 #define RW_MGR_GUARANTEED_READ_CONT	0x53
87 #define RW_MGR_GUARANTEED_WRITE	0x17
88 #define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1A
89 #define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1E
90 #define RW_MGR_GUARANTEED_WRITE_WAIT2	0x18
91 #define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1C
92 #define RW_MGR_IDLE	0x00
93 #define RW_MGR_IDLE_LOOP1	0x7C
94 #define RW_MGR_IDLE_LOOP2	0x7B
95 #define RW_MGR_INIT_RESET_0_CKE_0	0x6E
96 #define RW_MGR_INIT_RESET_1_CKE_0	0x73
97 #define RW_MGR_LFSR_WR_RD_BANK_0	0x21
98 #define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x24
99 #define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x23
100 #define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x22
101 #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x31
102 #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x20
103 #define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x35
104 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x38
105 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x37
106 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x36
107 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x45
108 #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x34
109 #define RW_MGR_MRS0_DLL_RESET	0x02
110 #define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
111 #define RW_MGR_MRS0_USER	0x07
112 #define RW_MGR_MRS0_USER_MIRR	0x0C
113 #define RW_MGR_MRS1	0x03
114 #define RW_MGR_MRS1_MIRR	0x09
115 #define RW_MGR_MRS2	0x04
116 #define RW_MGR_MRS2_MIRR	0x0A
117 #define RW_MGR_MRS3	0x05
118 #define RW_MGR_MRS3_MIRR	0x0B
119 #define RW_MGR_PRECHARGE_ALL	0x12
120 #define RW_MGR_READ_B2B	0x58
121 #define RW_MGR_READ_B2B_WAIT1	0x60
122 #define RW_MGR_READ_B2B_WAIT2	0x6A
123 #define RW_MGR_REFRESH_ALL	0x14
124 #define RW_MGR_RETURN	0x01
125 #define RW_MGR_SGLE_READ	0x7E
126 #define RW_MGR_ZQCL	0x06
127 
128 /* Sequencer defines configuration */
129 #define AFI_RATE_RATIO	1
130 #define CALIB_LFIFO_OFFSET	7
131 #define CALIB_VFIFO_OFFSET	5
132 #define ENABLE_SUPER_QUICK_CALIBRATION	0
133 #define IO_DELAY_PER_DCHAIN_TAP	25
134 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
135 #define IO_DELAY_PER_OPA_TAP	312
136 #define IO_DLL_CHAIN_LENGTH	8
137 #define IO_DQDQS_OUT_PHASE_MAX	0
138 #define IO_DQS_EN_DELAY_MAX	31
139 #define IO_DQS_EN_DELAY_OFFSET	0
140 #define IO_DQS_EN_PHASE_MAX	7
141 #define IO_DQS_IN_DELAY_MAX	31
142 #define IO_DQS_IN_RESERVE	4
143 #define IO_DQS_OUT_RESERVE	6
144 #define IO_IO_IN_DELAY_MAX	31
145 #define IO_IO_OUT1_DELAY_MAX	31
146 #define IO_IO_OUT2_DELAY_MAX	0
147 #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
148 #define MAX_LATENCY_COUNT_WIDTH	5
149 #define READ_VALID_FIFO_SIZE	16
150 #define REG_FILE_INIT_SEQ_SIGNATURE	0x55550483
151 #define RW_MGR_MEM_ADDRESS_MIRRORING	0
152 #define RW_MGR_MEM_DATA_MASK_WIDTH	5
153 #define RW_MGR_MEM_DATA_WIDTH	40
154 #define RW_MGR_MEM_DQ_PER_READ_DQS	8
155 #define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
156 #define RW_MGR_MEM_IF_READ_DQS_WIDTH	5
157 #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	5
158 #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
159 #define RW_MGR_MEM_NUMBER_OF_RANKS	1
160 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
161 #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
162 #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	5
163 #define TINIT_CNTR0_VAL	132
164 #define TINIT_CNTR1_VAL	32
165 #define TINIT_CNTR2_VAL	32
166 #define TRESET_CNTR0_VAL	132
167 #define TRESET_CNTR1_VAL	99
168 #define TRESET_CNTR2_VAL	10
169 
170 /* Sequencer ac_rom_init configuration */
171 const u32 ac_rom_init[] ={
172 	0x20700000,
173 	0x20780000,
174 	0x10080431,
175 	0x10080530,
176 	0x10090004,
177 	0x100a0008,
178 	0x100b0000,
179 	0x10380400,
180 	0x10080449,
181 	0x100804c8,
182 	0x100a0004,
183 	0x10090010,
184 	0x100b0000,
185 	0x30780000,
186 	0x38780000,
187 	0x30780000,
188 	0x10680000,
189 	0x106b0000,
190 	0x10280400,
191 	0x10480000,
192 	0x1c980000,
193 	0x1c9b0000,
194 	0x1c980008,
195 	0x1c9b0008,
196 	0x38f80000,
197 	0x3cf80000,
198 	0x38780000,
199 	0x18180000,
200 	0x18980000,
201 	0x13580000,
202 	0x135b0000,
203 	0x13580008,
204 	0x135b0008,
205 	0x33780000,
206 	0x10580008,
207 	0x10780000
208 };
209 
210 /* Sequencer inst_rom_init configuration */
211 const u32 inst_rom_init[] ={
212 	0x80000,
213 	0x80680,
214 	0x8180,
215 	0x8200,
216 	0x8280,
217 	0x8300,
218 	0x8380,
219 	0x8100,
220 	0x8480,
221 	0x8500,
222 	0x8580,
223 	0x8600,
224 	0x8400,
225 	0x800,
226 	0x8680,
227 	0x880,
228 	0xa680,
229 	0x80680,
230 	0x900,
231 	0x80680,
232 	0x980,
233 	0x8680,
234 	0x80680,
235 	0xb68,
236 	0xcce8,
237 	0xae8,
238 	0x8ce8,
239 	0xb88,
240 	0xec88,
241 	0xa08,
242 	0xac88,
243 	0x80680,
244 	0xce00,
245 	0xcd80,
246 	0xe700,
247 	0xc00,
248 	0x20ce0,
249 	0x20ce0,
250 	0x20ce0,
251 	0x20ce0,
252 	0xd00,
253 	0x680,
254 	0x680,
255 	0x680,
256 	0x680,
257 	0x60e80,
258 	0x61080,
259 	0x61080,
260 	0x61080,
261 	0xa680,
262 	0x8680,
263 	0x80680,
264 	0xce00,
265 	0xcd80,
266 	0xe700,
267 	0xc00,
268 	0x30ce0,
269 	0x30ce0,
270 	0x30ce0,
271 	0x30ce0,
272 	0xd00,
273 	0x680,
274 	0x680,
275 	0x680,
276 	0x680,
277 	0x70e80,
278 	0x71080,
279 	0x71080,
280 	0x71080,
281 	0xa680,
282 	0x8680,
283 	0x80680,
284 	0x1158,
285 	0x6d8,
286 	0x80680,
287 	0x1168,
288 	0x7e8,
289 	0x7e8,
290 	0x87e8,
291 	0x40fe8,
292 	0x410e8,
293 	0x410e8,
294 	0x410e8,
295 	0x1168,
296 	0x7e8,
297 	0x7e8,
298 	0xa7e8,
299 	0x80680,
300 	0x40e88,
301 	0x41088,
302 	0x41088,
303 	0x41088,
304 	0x40f68,
305 	0x410e8,
306 	0x410e8,
307 	0x410e8,
308 	0xa680,
309 	0x40fe8,
310 	0x410e8,
311 	0x410e8,
312 	0x410e8,
313 	0x41008,
314 	0x41088,
315 	0x41088,
316 	0x41088,
317 	0x1100,
318 	0xc680,
319 	0x8680,
320 	0xe680,
321 	0x80680,
322 	0x0,
323 	0x0,
324 	0xa000,
325 	0x8000,
326 	0x80000,
327 	0x80,
328 	0x80,
329 	0x80,
330 	0x80,
331 	0xa080,
332 	0x8080,
333 	0x80080,
334 	0x9180,
335 	0x8680,
336 	0xa680,
337 	0x80680,
338 	0x40f08,
339 	0x80680
340 };
341 
342 #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
343