1 /* 2 * Copyright Altera Corporation (C) 2012-2014. All rights reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* This file is generated by Preloader Generator */ 8 9 #ifndef _PRELOADER_PLL_CONFIG_H_ 10 #define _PRELOADER_PLL_CONFIG_H_ 11 12 /* PLL configuration data */ 13 /* Main PLL */ 14 #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) 15 #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) 16 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) 17 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) 18 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) 19 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) 20 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) 21 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) 22 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) 23 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) 24 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) 25 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) 26 #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) 27 #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) 28 #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) 29 /* 30 * To tell where is the clock source: 31 * 0 = MAINPLL 32 * 1 = PERIPHPLL 33 */ 34 #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) 35 #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) 36 37 /* Peripheral PLL */ 38 #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) 39 #define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) 40 /* 41 * To tell where is the VCOs source: 42 * 0 = EOSC1 43 * 1 = EOSC2 44 * 2 = F2S 45 */ 46 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) 47 #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) 48 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511) 49 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) 50 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) 51 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) 52 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) 53 #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) 54 #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4) 55 #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) 56 #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) 57 #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) 58 /* 59 * To tell where is the clock source: 60 * 0 = F2S_PERIPH_REF_CLK 61 * 1 = MAIN_CLK 62 * 2 = PERIPH_CLK 63 */ 64 #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) 65 #define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) 66 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) 67 68 /* SDRAM PLL */ 69 #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) 70 #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) 71 72 /* 73 * To tell where is the VCOs source: 74 * 0 = EOSC1 75 * 1 = EOSC2 76 * 2 = F2S 77 */ 78 #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) 79 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) 80 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) 81 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) 82 #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) 83 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) 84 #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) 85 #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) 86 #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) 87 88 /* Info for driver */ 89 #define CONFIG_HPS_CLK_OSC1_HZ (25000000) 90 #define CONFIG_HPS_CLK_OSC2_HZ (25000000) 91 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 92 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 93 #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) 94 #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) 95 #define CONFIG_HPS_CLK_SDRVCO_HZ (666666666) 96 #define CONFIG_HPS_CLK_EMAC0_HZ (250000000) 97 #define CONFIG_HPS_CLK_EMAC1_HZ (250000000) 98 #define CONFIG_HPS_CLK_USBCLK_HZ (200000000) 99 #define CONFIG_HPS_CLK_NAND_HZ (50000000) 100 #define CONFIG_HPS_CLK_SDMMC_HZ (200000000) 101 #define CONFIG_HPS_CLK_QSPI_HZ (400000000) 102 #define CONFIG_HPS_CLK_SPIM_HZ (200000000) 103 #define CONFIG_HPS_CLK_CAN0_HZ (100000000) 104 #define CONFIG_HPS_CLK_CAN1_HZ (100000000) 105 #define CONFIG_HPS_CLK_GPIODB_HZ (32000) 106 #define CONFIG_HPS_CLK_L4_MP_HZ (100000000) 107 #define CONFIG_HPS_CLK_L4_SP_HZ (100000000) 108 109 #endif /* _PRELOADER_PLL_CONFIG_H_ */ 110