1f0892401SMarek Vasut /* 2*f6badb0dSMarek Vasut * Altera SoCFPGA Clock and PLL configuration 3f0892401SMarek Vasut * 4f0892401SMarek Vasut * SPDX-License-Identifier: BSD-3-Clause 5f0892401SMarek Vasut */ 6f0892401SMarek Vasut 7*f6badb0dSMarek Vasut #ifndef __SOCFPGA_PLL_CONFIG_H__ 8*f6badb0dSMarek Vasut #define __SOCFPGA_PLL_CONFIG_H__ 9f0892401SMarek Vasut 10*f6badb0dSMarek Vasut #define CONFIG_HPS_DBCTRL_STAYOSC1 1 11f0892401SMarek Vasut 12*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 13*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 14*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 15*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 16*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 17*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 18*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 19*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 20*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 21*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 22*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 23*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 24*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 25*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 26*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 27*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 28*f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 29f0892401SMarek Vasut 30*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1 31*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 32*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 33*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 34*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 35*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 36*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 37*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 38*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 39*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 40*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 41*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 42*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 43*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 44*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 45*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 46*f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 47f0892401SMarek Vasut 48*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 49*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 50*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 51*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 52*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 53*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 54*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 55*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 56*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 57*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 58*f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 59f0892401SMarek Vasut 60*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_OSC1_HZ 25000000 61*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_OSC2_HZ 25000000 62f0892401SMarek Vasut #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 63f0892401SMarek Vasut #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 64*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 65*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 66*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 67*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 68*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 69*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 70*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_NAND_HZ 50000000 71*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 72*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_QSPI_HZ 400000000 73*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_SPIM_HZ 200000000 74*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_CAN0_HZ 100000000 75*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_CAN1_HZ 100000000 76*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_GPIODB_HZ 32000 77*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_L4_MP_HZ 100000000 78*f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 79f0892401SMarek Vasut 80*f6badb0dSMarek Vasut #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 81*f6badb0dSMarek Vasut #define CONFIG_HPS_ALTERAGRP_MAINCLK 3 82*f6badb0dSMarek Vasut #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 83*f6badb0dSMarek Vasut 84*f6badb0dSMarek Vasut 85*f6badb0dSMarek Vasut #endif /* __SOCFPGA_PLL_CONFIG_H__ */ 86