1*f0892401SMarek Vasut /* 2*f0892401SMarek Vasut * Copyright Altera Corporation (C) 2012-2014. All rights reserved 3*f0892401SMarek Vasut * 4*f0892401SMarek Vasut * SPDX-License-Identifier: BSD-3-Clause 5*f0892401SMarek Vasut */ 6*f0892401SMarek Vasut 7*f0892401SMarek Vasut /* This file is generated by Preloader Generator */ 8*f0892401SMarek Vasut 9*f0892401SMarek Vasut #ifndef _PRELOADER_PLL_CONFIG_H_ 10*f0892401SMarek Vasut #define _PRELOADER_PLL_CONFIG_H_ 11*f0892401SMarek Vasut 12*f0892401SMarek Vasut /* PLL configuration data */ 13*f0892401SMarek Vasut /* Main PLL */ 14*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) 15*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) 16*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) 17*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) 18*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) 19*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) 20*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) 21*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) 22*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) 23*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) 24*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) 25*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) 26*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) 27*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) 28*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) 29*f0892401SMarek Vasut /* 30*f0892401SMarek Vasut * To tell where is the clock source: 31*f0892401SMarek Vasut * 0 = MAINPLL 32*f0892401SMarek Vasut * 1 = PERIPHPLL 33*f0892401SMarek Vasut */ 34*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) 35*f0892401SMarek Vasut #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) 36*f0892401SMarek Vasut 37*f0892401SMarek Vasut /* Peripheral PLL */ 38*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) 39*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) 40*f0892401SMarek Vasut /* 41*f0892401SMarek Vasut * To tell where is the VCOs source: 42*f0892401SMarek Vasut * 0 = EOSC1 43*f0892401SMarek Vasut * 1 = EOSC2 44*f0892401SMarek Vasut * 2 = F2S 45*f0892401SMarek Vasut */ 46*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) 47*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) 48*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511) 49*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) 50*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) 51*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) 52*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) 53*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) 54*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4) 55*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) 56*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) 57*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) 58*f0892401SMarek Vasut /* 59*f0892401SMarek Vasut * To tell where is the clock source: 60*f0892401SMarek Vasut * 0 = F2S_PERIPH_REF_CLK 61*f0892401SMarek Vasut * 1 = MAIN_CLK 62*f0892401SMarek Vasut * 2 = PERIPH_CLK 63*f0892401SMarek Vasut */ 64*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) 65*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) 66*f0892401SMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) 67*f0892401SMarek Vasut 68*f0892401SMarek Vasut /* SDRAM PLL */ 69*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) 70*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) 71*f0892401SMarek Vasut 72*f0892401SMarek Vasut /* 73*f0892401SMarek Vasut * To tell where is the VCOs source: 74*f0892401SMarek Vasut * 0 = EOSC1 75*f0892401SMarek Vasut * 1 = EOSC2 76*f0892401SMarek Vasut * 2 = F2S 77*f0892401SMarek Vasut */ 78*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) 79*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) 80*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) 81*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) 82*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) 83*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) 84*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) 85*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) 86*f0892401SMarek Vasut #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) 87*f0892401SMarek Vasut 88*f0892401SMarek Vasut /* Info for driver */ 89*f0892401SMarek Vasut #define CONFIG_HPS_CLK_OSC1_HZ (25000000) 90*f0892401SMarek Vasut #define CONFIG_HPS_CLK_OSC2_HZ (25000000) 91*f0892401SMarek Vasut #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 92*f0892401SMarek Vasut #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 93*f0892401SMarek Vasut #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) 94*f0892401SMarek Vasut #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) 95*f0892401SMarek Vasut #define CONFIG_HPS_CLK_SDRVCO_HZ (666666666) 96*f0892401SMarek Vasut #define CONFIG_HPS_CLK_EMAC0_HZ (250000000) 97*f0892401SMarek Vasut #define CONFIG_HPS_CLK_EMAC1_HZ (250000000) 98*f0892401SMarek Vasut #define CONFIG_HPS_CLK_USBCLK_HZ (200000000) 99*f0892401SMarek Vasut #define CONFIG_HPS_CLK_NAND_HZ (50000000) 100*f0892401SMarek Vasut #define CONFIG_HPS_CLK_SDMMC_HZ (200000000) 101*f0892401SMarek Vasut #define CONFIG_HPS_CLK_QSPI_HZ (400000000) 102*f0892401SMarek Vasut #define CONFIG_HPS_CLK_SPIM_HZ (200000000) 103*f0892401SMarek Vasut #define CONFIG_HPS_CLK_CAN0_HZ (100000000) 104*f0892401SMarek Vasut #define CONFIG_HPS_CLK_CAN1_HZ (100000000) 105*f0892401SMarek Vasut #define CONFIG_HPS_CLK_GPIODB_HZ (32000) 106*f0892401SMarek Vasut #define CONFIG_HPS_CLK_L4_MP_HZ (100000000) 107*f0892401SMarek Vasut #define CONFIG_HPS_CLK_L4_SP_HZ (100000000) 108*f0892401SMarek Vasut 109*f0892401SMarek Vasut #endif /* _PRELOADER_PLL_CONFIG_H_ */ 110