1f0892401SMarek Vasut /* 2f6badb0dSMarek Vasut * Altera SoCFPGA Clock and PLL configuration 3f0892401SMarek Vasut * 4f0892401SMarek Vasut * SPDX-License-Identifier: BSD-3-Clause 5f0892401SMarek Vasut */ 6f0892401SMarek Vasut 7f6badb0dSMarek Vasut #ifndef __SOCFPGA_PLL_CONFIG_H__ 8f6badb0dSMarek Vasut #define __SOCFPGA_PLL_CONFIG_H__ 9f0892401SMarek Vasut 10f6badb0dSMarek Vasut #define CONFIG_HPS_DBCTRL_STAYOSC1 1 11f0892401SMarek Vasut 12f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 13f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 14f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 15f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 16f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 17f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 18f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 19f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 20f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 21f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 22f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 23f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 24f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 25f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 26f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 27f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 28f6badb0dSMarek Vasut #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 29f0892401SMarek Vasut 30f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1 31f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 32f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 33f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 34*b0808b91Sshengjiangwu #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 35f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 36f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 37f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 38f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 39f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 40f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 41f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 42f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 43f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 44f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 45f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 46f6badb0dSMarek Vasut #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 47f0892401SMarek Vasut 48f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 49f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 50f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 51f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 52f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 53f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 54f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 55f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 56f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 57f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 58f6badb0dSMarek Vasut #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 59f0892401SMarek Vasut 60f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_OSC1_HZ 25000000 61f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_OSC2_HZ 25000000 62f0892401SMarek Vasut #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 63f0892401SMarek Vasut #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 64f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 65f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 66f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 67f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_EMAC0_HZ 250000000 68f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 69f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 70f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_NAND_HZ 50000000 71f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 72f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_QSPI_HZ 400000000 73f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_SPIM_HZ 200000000 74f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_CAN0_HZ 100000000 75f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_CAN1_HZ 100000000 76f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_GPIODB_HZ 32000 77f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_L4_MP_HZ 100000000 78f6badb0dSMarek Vasut #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 79f0892401SMarek Vasut 80f6badb0dSMarek Vasut #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 81f6badb0dSMarek Vasut #define CONFIG_HPS_ALTERAGRP_MAINCLK 3 82f6badb0dSMarek Vasut #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 83f6badb0dSMarek Vasut 84f6badb0dSMarek Vasut 85f6badb0dSMarek Vasut #endif /* __SOCFPGA_PLL_CONFIG_H__ */ 86