1/* 2 * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3 * Copyright (C) 2011, 2012 Renesas Solutions Corp. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7#include <config.h> 8#include <version.h> 9#include <asm/processor.h> 10#include <asm/macro.h> 11 12#include <asm/processor.h> 13 14 .global lowlevel_init 15 16 .text 17 .align 2 18 19lowlevel_init: 20 21 /* WDT */ 22 write32 WDTCSR_A, WDTCSR_D 23 24 /* MMU */ 25 write32 MMUCR_A, MMUCR_D 26 27 write32 FRQCR2_A, FRQCR2_D 28 write32 FRQCR0_A, FRQCR0_D 29 30 write32 CS0CTRL_A, CS0CTRL_D 31 write32 CS1CTRL_A, CS1CTRL_D 32 write32 CS0CTRL2_A, CS0CTRL2_D 33 34 write32 CSPWCR0_A, CSPWCR0_D 35 write32 CSPWCR1_A, CSPWCR1_D 36 write32 CS1GDST_A, CS1GDST_D 37 38 # clock mode check 39 mov.l MODEMR, r1 40 mov.l @r1, r0 41 and #6, r0 /* Check 1 and 2 bit.*/ 42 cmp/eq #2, r0 /* 0x02 is 533Mhz mode */ 43 bt init_lbsc_533 44 45init_lbsc_400: 46 47 write32 CSWCR0_A, CSWCR0_D_400 48 write32 CSWCR1_A, CSWCR1_D 49 50 bra init_dbsc3_400_pad 51 nop 52 53 .align 2 54 55MODEMR: .long 0xFFCC0020 56WDTCSR_A: .long 0xFFCC0004 57WDTCSR_D: .long 0xA5000000 58MMUCR_A: .long 0xFF000010 59MMUCR_D: .long 0x00000004 60 61FRQCR2_A: .long 0xFFC80008 62FRQCR2_D: .long 0x00000000 63FRQCR0_A: .long 0xFFC80000 64FRQCR0_D: .long 0xCF000001 65 66CS0CTRL_A: .long 0xFF800200 67CS0CTRL_D: .long 0x00000020 68CS1CTRL_A: .long 0xFF800204 69CS1CTRL_D: .long 0x00000020 70 71CS0CTRL2_A: .long 0xFF800220 72CS0CTRL2_D: .long 0x00004000 73 74CSPWCR0_A: .long 0xFF800280 75CSPWCR0_D: .long 0x00000000 76CSPWCR1_A: .long 0xFF800284 77CSPWCR1_D: .long 0x00000000 78CS1GDST_A: .long 0xFF8002C0 79CS1GDST_D: .long 0x00000011 80 81init_lbsc_533: 82 83 write32 CSWCR0_A, CSWCR0_D_533 84 write32 CSWCR1_A, CSWCR1_D 85 86 bra init_dbsc3_533_pad 87 nop 88 89 .align 2 90 91CSWCR0_A: .long 0xFF800230 92CSWCR0_D_533: .long 0x01120104 93CSWCR0_D_400: .long 0x02120114 94CSWCR1_A: .long 0xFF800234 95CSWCR1_D: .long 0x077F077F 96 97init_dbsc3_400_pad: 98 99 write32 DBPDCNT3_A, DBPDCNT3_D 100 wait_timer WAIT_200US_400 101 102 write32 DBPDCNT0_A, DBPDCNT0_D_400 103 write32 DBPDCNT3_A, DBPDCNT3_D0 104 write32 DBPDCNT1_A, DBPDCNT1_D 105 106 write32 DBPDCNT3_A, DBPDCNT3_D1 107 wait_timer WAIT_32MCLK 108 109 write32 DBPDCNT3_A, DBPDCNT3_D2 110 wait_timer WAIT_100US_400 111 112 write32 DBPDCNT3_A, DBPDCNT3_D3 113 wait_timer WAIT_16MCLK 114 115 write32 DBPDCNT3_A, DBPDCNT3_D4 116 wait_timer WAIT_200US_400 117 118 write32 DBPDCNT3_A, DBPDCNT3_D5 119 wait_timer WAIT_1MCLK 120 121 write32 DBPDCNT3_A, DBPDCNT3_D6 122 wait_timer WAIT_10KMCLK 123 124 bra init_dbsc3_ctrl_400 125 nop 126 127 .align 2 128 129init_dbsc3_533_pad: 130 131 write32 DBPDCNT3_A, DBPDCNT3_D 132 wait_timer WAIT_200US_533 133 134 write32 DBPDCNT0_A, DBPDCNT0_D_533 135 write32 DBPDCNT3_A, DBPDCNT3_D0 136 write32 DBPDCNT1_A, DBPDCNT1_D 137 138 write32 DBPDCNT3_A, DBPDCNT3_D1 139 wait_timer WAIT_32MCLK 140 141 write32 DBPDCNT3_A, DBPDCNT3_D2 142 wait_timer WAIT_100US_533 143 144 write32 DBPDCNT3_A, DBPDCNT3_D3 145 wait_timer WAIT_16MCLK 146 147 write32 DBPDCNT3_A, DBPDCNT3_D4 148 wait_timer WAIT_200US_533 149 150 write32 DBPDCNT3_A, DBPDCNT3_D5 151 wait_timer WAIT_1MCLK 152 153 write32 DBPDCNT3_A, DBPDCNT3_D6 154 wait_timer WAIT_10KMCLK 155 156 bra init_dbsc3_ctrl_533 157 nop 158 159 .align 2 160 161WAIT_200US_400: .long 40000 162WAIT_200US_533: .long 53300 163WAIT_100US_400: .long 20000 164WAIT_100US_533: .long 26650 165WAIT_32MCLK: .long 32 166WAIT_16MCLK: .long 16 167WAIT_1MCLK: .long 1 168WAIT_10KMCLK: .long 10000 169 170DBPDCNT0_A: .long 0xFE800200 171DBPDCNT0_D_533: .long 0x00010245 172DBPDCNT0_D_400: .long 0x00010235 173DBPDCNT1_A: .long 0xFE800204 174DBPDCNT1_D: .long 0x00000014 175DBPDCNT3_A: .long 0xFE80020C 176DBPDCNT3_D: .long 0x80000000 177DBPDCNT3_D0: .long 0x800F0000 178DBPDCNT3_D1: .long 0x800F1000 179DBPDCNT3_D2: .long 0x820F1000 180DBPDCNT3_D3: .long 0x860F1000 181DBPDCNT3_D4: .long 0x870F1000 182DBPDCNT3_D5: .long 0x870F3000 183DBPDCNT3_D6: .long 0x870F7000 184 185init_dbsc3_ctrl_400: 186 187 write32 DBKIND_A, DBKIND_D 188 write32 DBCONF_A, DBCONF_D 189 190 write32 DBTR0_A, DBTR0_D_400 191 write32 DBTR1_A, DBTR1_D_400 192 write32 DBTR2_A, DBTR2_D 193 write32 DBTR3_A, DBTR3_D_400 194 write32 DBTR4_A, DBTR4_D_400 195 write32 DBTR5_A, DBTR5_D_400 196 write32 DBTR6_A, DBTR6_D_400 197 write32 DBTR7_A, DBTR7_D 198 write32 DBTR8_A, DBTR8_D_400 199 write32 DBTR9_A, DBTR9_D 200 write32 DBTR10_A, DBTR10_D_400 201 write32 DBTR11_A, DBTR11_D 202 write32 DBTR12_A, DBTR12_D_400 203 write32 DBTR13_A, DBTR13_D_400 204 write32 DBTR14_A, DBTR14_D 205 write32 DBTR15_A, DBTR15_D 206 write32 DBTR16_A, DBTR16_D_400 207 write32 DBTR17_A, DBTR17_D_400 208 write32 DBTR18_A, DBTR18_D_400 209 210 write32 DBBL_A, DBBL_D 211 write32 DBRNK0_A, DBRNK0_D 212 213 write32 DBCMD_A, DBCMD_D0_400 214 write32 DBCMD_A, DBCMD_D1 215 write32 DBCMD_A, DBCMD_D2 216 write32 DBCMD_A, DBCMD_D3 217 write32 DBCMD_A, DBCMD_D4 218 write32 DBCMD_A, DBCMD_D5_400 219 write32 DBCMD_A, DBCMD_D6 220 write32 DBCMD_A, DBCMD_D7 221 write32 DBCMD_A, DBCMD_D8 222 write32 DBCMD_A, DBCMD_D9_400 223 write32 DBCMD_A, DBCMD_D10 224 write32 DBCMD_A, DBCMD_D11 225 write32 DBCMD_A, DBCMD_D12 226 227 write32 DBRFCNF0_A, DBRFCNF0_D 228 write32 DBRFCNF1_A, DBRFCNF1_D_400 229 write32 DBRFCNF2_A, DBRFCNF2_D 230 write32 DBRFEN_A, DBRFEN_D 231 write32 DBACEN_A, DBACEN_D 232 write32 DBACEN_A, DBACEN_D 233 234 /* Dummy read */ 235 mov.l DBWAIT_A, r1 236 synco 237 mov.l @r1, r0 238 synco 239 240 /* Dummy read */ 241 mov.l SDRAM_A, r1 242 synco 243 mov.l @r1, r0 244 synco 245 246 /* need sleep 186A0 */ 247 248 bra finish_init_sh7734 249 nop 250 251 .align 2 252 253init_dbsc3_ctrl_533: 254 255 write32 DBKIND_A, DBKIND_D 256 write32 DBCONF_A, DBCONF_D 257 258 write32 DBTR0_A, DBTR0_D_533 259 write32 DBTR1_A, DBTR1_D_533 260 write32 DBTR2_A, DBTR2_D 261 write32 DBTR3_A, DBTR3_D_533 262 write32 DBTR4_A, DBTR4_D_533 263 write32 DBTR5_A, DBTR5_D_533 264 write32 DBTR6_A, DBTR6_D_533 265 write32 DBTR7_A, DBTR7_D 266 write32 DBTR8_A, DBTR8_D_533 267 write32 DBTR9_A, DBTR9_D 268 write32 DBTR10_A, DBTR10_D_533 269 write32 DBTR11_A, DBTR11_D 270 write32 DBTR12_A, DBTR12_D_533 271 write32 DBTR13_A, DBTR13_D_533 272 write32 DBTR14_A, DBTR14_D 273 write32 DBTR15_A, DBTR15_D 274 write32 DBTR16_A, DBTR16_D_533 275 write32 DBTR17_A, DBTR17_D_533 276 write32 DBTR18_A, DBTR18_D_533 277 278 write32 DBBL_A, DBBL_D 279 write32 DBRNK0_A, DBRNK0_D 280 281 write32 DBCMD_A, DBCMD_D0_533 282 write32 DBCMD_A, DBCMD_D1 283 write32 DBCMD_A, DBCMD_D2 284 write32 DBCMD_A, DBCMD_D3 285 write32 DBCMD_A, DBCMD_D4 286 write32 DBCMD_A, DBCMD_D5_533 287 write32 DBCMD_A, DBCMD_D6 288 write32 DBCMD_A, DBCMD_D7 289 write32 DBCMD_A, DBCMD_D8 290 write32 DBCMD_A, DBCMD_D9_533 291 write32 DBCMD_A, DBCMD_D10 292 write32 DBCMD_A, DBCMD_D11 293 write32 DBCMD_A, DBCMD_D12 294 295 write32 DBRFCNF0_A, DBRFCNF0_D 296 write32 DBRFCNF1_A, DBRFCNF1_D_533 297 write32 DBRFCNF2_A, DBRFCNF2_D 298 write32 DBRFEN_A, DBRFEN_D 299 write32 DBACEN_A, DBACEN_D 300 write32 DBACEN_A, DBACEN_D 301 302 /* Dummy read */ 303 mov.l DBWAIT_A, r1 304 synco 305 mov.l @r1, r0 306 synco 307 308 /* Dummy read */ 309 mov.l SDRAM_A, r1 310 synco 311 mov.l @r1, r0 312 synco 313 314 /* need sleep 186A0 */ 315 316 bra finish_init_sh7734 317 nop 318 319 .align 2 320 321DBKIND_A: .long 0xFE800020 322DBKIND_D: .long 0x00000005 323DBCONF_A: .long 0xFE800024 324DBCONF_D: .long 0x0D020A01 325 326DBTR0_A: .long 0xFE800040 327DBTR0_D_533:.long 0x00000004 328DBTR0_D_400:.long 0x00000003 329DBTR1_A: .long 0xFE800044 330DBTR1_D_533:.long 0x00000003 331DBTR1_D_400:.long 0x00000002 332DBTR2_A: .long 0xFE800048 333DBTR2_D: .long 0x00000000 334DBTR3_A: .long 0xFE800050 335DBTR3_D_533:.long 0x00000004 336DBTR3_D_400:.long 0x00000003 337 338DBTR4_A: .long 0xFE800054 339DBTR4_D_533:.long 0x00050004 340DBTR4_D_400:.long 0x00050003 341 342DBTR5_A: .long 0xFE800058 343DBTR5_D_533:.long 0x0000000F 344DBTR5_D_400:.long 0x0000000B 345 346DBTR6_A: .long 0xFE80005C 347DBTR6_D_533:.long 0x0000000B 348DBTR6_D_400:.long 0x00000008 349 350DBTR7_A: .long 0xFE800060 351DBTR7_D: .long 0x00000002 352 353DBTR8_A: .long 0xFE800064 354DBTR8_D_533:.long 0x0000000D 355DBTR8_D_400:.long 0x0000000A 356 357DBTR9_A: .long 0xFE800068 358DBTR9_D: .long 0x00000002 359 360DBTR10_A: .long 0xFE80006C 361DBTR10_D_533:.long 0x00000004 362DBTR10_D_400:.long 0x00000003 363 364DBTR11_A: .long 0xFE800070 365DBTR11_D: .long 0x00000008 366 367DBTR12_A: .long 0xFE800074 368DBTR12_D_533:.long 0x00000009 369DBTR12_D_400:.long 0x00000008 370 371DBTR13_A: .long 0xFE800078 372DBTR13_D_533:.long 0x00000022 373DBTR13_D_400:.long 0x0000001A 374 375DBTR14_A: .long 0xFE80007C 376DBTR14_D: .long 0x00070002 377 378DBTR15_A: .long 0xFE800080 379DBTR15_D: .long 0x00000003 380 381DBTR16_A: .long 0xFE800084 382DBTR16_D_533:.long 0x120A1001 383DBTR16_D_400:.long 0x12091001 384 385DBTR17_A: .long 0xFE800088 386DBTR17_D_533:.long 0x00040000 387DBTR17_D_400:.long 0x00030000 388 389DBTR18_A: .long 0xFE80008C 390DBTR18_D_533:.long 0x02010200 391DBTR18_D_400:.long 0x02000207 392 393DBBL_A: .long 0xFE8000B0 394DBBL_D: .long 0x00000000 395 396DBRNK0_A: .long 0xFE800100 397DBRNK0_D: .long 0x00000001 398 399DBCMD_A: .long 0xFE800018 400DBCMD_D0_533: .long 0x1100006B 401DBCMD_D0_400: .long 0x11000050 402DBCMD_D1: .long 0x0B000000 403DBCMD_D2: .long 0x2A004000 404DBCMD_D3: .long 0x2B006000 405DBCMD_D4: .long 0x29002044 406DBCMD_D5_533: .long 0x28000743 407DBCMD_D5_400: .long 0x28000533 408DBCMD_D6: .long 0x0B000000 409DBCMD_D7: .long 0x0C000000 410DBCMD_D8: .long 0x0C000000 411DBCMD_D9_533: .long 0x28000643 412DBCMD_D9_400: .long 0x28000433 413DBCMD_D10: .long 0x000000C8 414DBCMD_D11: .long 0x290023C4 415DBCMD_D12: .long 0x29002004 416 417DBRFCNF0_A: .long 0xFE8000E0 418DBRFCNF0_D: .long 0x000001FF 419DBRFCNF1_A: .long 0xFE8000E4 420DBRFCNF1_D_533: .long 0x00000805 421DBRFCNF1_D_400: .long 0x00000618 422 423DBRFCNF2_A: .long 0xFE8000E8 424DBRFCNF2_D: .long 0x00000000 425 426DBRFEN_A: .long 0xFE800014 427DBRFEN_D: .long 0x00000001 428 429DBACEN_A: .long 0xFE800010 430DBACEN_D: .long 0x00000001 431 432DBWAIT_A: .long 0xFE80001C 433SDRAM_A: .long 0x0C000000 434 435finish_init_sh7734: 436 write32 CCR_A, CCR_D 437 438 stc sr, r0 439 mov.l SR_MASK_D, r1 440 and r1, r0 441 ldc r0, sr 442 443 rts 444 nop 445 446 .align 2 447 448CCR_A: .long 0xFF00001C 449CCR_D: .long 0x0000090B 450SR_MASK_D: .long 0xEFFFFF0F 451