1 /*
2  * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3  * Copyright (C) 2012 Renesas Solutions Corp.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/processor.h>
11 #include <netdev.h>
12 #include <i2c.h>
13 
14 DECLARE_GLOBAL_DATA_PTR;
15 
16 #define MODEMR			(0xFFCC0020)
17 #define MODEMR_MASK		(0x6)
18 #define MODEMR_533MHZ	(0x2)
19 
20 int checkboard(void)
21 {
22 	u32 r = readl(MODEMR);
23 	if ((r & MODEMR_MASK) & MODEMR_533MHZ)
24 		puts("CPU Clock: 533MHz\n");
25 	else
26 		puts("CPU Clock: 400MHz\n");
27 
28 	puts("BOARD: Alpha Project. AP-SH4A-4A\n");
29 	return 0;
30 }
31 
32 #define MSTPSR1			(0xFFC80044)
33 #define MSTPCR1			(0xFFC80034)
34 #define MSTPSR1_GETHER	(1 << 14)
35 
36 /* IPSR3 */
37 #define ET0_ETXD0 (0x4 << 3)
38 #define ET0_GTX_CLK_A (0x4 << 6)
39 #define ET0_ETXD1_A (0x4 << 9)
40 #define ET0_ETXD2_A (0x4 << 12)
41 #define ET0_ETXD3_A (0x4 << 15)
42 #define ET0_ETXD4 (0x3 << 18)
43 #define ET0_ETXD5_A (0x5 << 21)
44 #define ET0_ETXD6_A (0x5 << 24)
45 #define ET0_ETXD7 (0x4 << 27)
46 #define IPSR3_ETH_ENABLE \
47 	(ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
48 	ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
49 
50 /* IPSR4 */
51 #define ET0_ERXD7	(0x4)
52 #define ET0_RX_DV	(0x4 << 3)
53 #define ET0_RX_ER	(0x4 << 6)
54 #define ET0_CRS		(0x4 << 9)
55 #define ET0_COL		(0x4 << 12)
56 #define ET0_MDC		(0x4 << 15)
57 #define ET0_MDIO_A	(0x3 << 18)
58 #define ET0_LINK_A	(0x3 << 20)
59 #define ET0_PHY_INT_A (0x3 << 24)
60 
61 #define IPSR4_ETH_ENABLE \
62 	(ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
63 	ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
64 
65 /* IPSR8 */
66 #define ET0_ERXD0	(0x4 << 20)
67 #define ET0_ERXD1	(0x4 << 23)
68 #define ET0_ERXD2_A (0x3 << 26)
69 #define ET0_ERXD3_A (0x3 << 28)
70 #define IPSR8_ETH_ENABLE \
71 	(ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
72 
73 /* IPSR10 */
74 #define RX4_D	(0x1 << 22)
75 #define TX4_D	(0x1 << 23)
76 #define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
77 
78 /* IPSR11 */
79 #define ET0_ERXD4	(0x4 <<  4)
80 #define ET0_ERXD5	(0x4 <<  7)
81 #define ET0_ERXD6	(0x3 << 10)
82 #define ET0_TX_EN	(0x2 << 19)
83 #define ET0_TX_ER	(0x2 << 21)
84 #define ET0_TX_CLK_A (0x4 << 23)
85 #define ET0_RX_CLK_A (0x3 << 26)
86 #define IPSR11_ETH_ENABLE \
87 	(ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
88 	ET0_TX_CLK_A | ET0_RX_CLK_A)
89 
90 #define GPSR1_INIT (0xFFFF7FFF)
91 #define GPSR2_INIT (0x4005FEFF)
92 #define GPSR3_INIT (0x2EFFFFFF)
93 #define GPSR4_INIT (0xC7000000)
94 
95 int board_init(void)
96 {
97 	u32 data;
98 
99 	/* Set IPSR register */
100 	data = readl(IPSR3);
101 	data |= IPSR3_ETH_ENABLE;
102 	writel(~data, PMMR);
103 	writel(data, IPSR3);
104 
105 	data = readl(IPSR4);
106 	data |= IPSR4_ETH_ENABLE;
107 	writel(~data, PMMR);
108 	writel(data, IPSR4);
109 
110 	data = readl(IPSR8);
111 	data |= IPSR8_ETH_ENABLE;
112 	writel(~data, PMMR);
113 	writel(data, IPSR8);
114 
115 	data = readl(IPSR10);
116 	data |= IPSR10_SCIF_ENABLE;
117 	writel(~data, PMMR);
118 	writel(data, IPSR10);
119 
120 	data = readl(IPSR11);
121 	data |= IPSR11_ETH_ENABLE;
122 	writel(~data, PMMR);
123 	writel(data, IPSR11);
124 
125 	/* GPIO select */
126 	data = GPSR1_INIT;
127 	writel(~data, PMMR);
128 	writel(data, GPSR1);
129 
130 	data = GPSR2_INIT;
131 	writel(~data, PMMR);
132 	writel(data, GPSR2);
133 
134 	data = GPSR3_INIT;
135 	writel(~data, PMMR);
136 	writel(data, GPSR3);
137 
138 	data = GPSR4_INIT;
139 	writel(~data, PMMR);
140 	writel(data, GPSR4);
141 
142 	data = 0x0;
143 	writel(~data, PMMR);
144 	writel(data, GPSR5);
145 
146 	/* mode select */
147 	data = MODESEL2_INIT;
148 	writel(~data, PMMR);
149 	writel(data, MODESEL2);
150 
151 #if defined(CONFIG_SH_ETHER)
152 	u32 r = readl(MSTPSR1);
153 	if (r & MSTPSR1_GETHER)
154 		writel((r & ~MSTPSR1_GETHER), MSTPCR1);
155 #endif
156 	return 0;
157 }
158 
159 int board_late_init(void)
160 {
161 	u8 mac[6];
162 
163 	/* Read Mac Address and set*/
164 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
165 	i2c_set_bus_num(CONFIG_SYS_I2C_MODULE);
166 
167 	/* Read MAC address */
168 	i2c_read(0x50, 0x0, 0, mac, 6);
169 
170 	if (is_valid_ethaddr(mac))
171 		eth_setenv_enetaddr("ethaddr", mac);
172 
173 	return 0;
174 }
175 
176 int dram_init(void)
177 {
178 	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
179 	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
180 	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
181 
182 	return 0;
183 }
184